Network Acceleration

• 
  Jeffrey Fong, Xiang Wang, Yaxuan Qi, Jun Li, Weirong Jiang: ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification. 1-8
• 
  John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers: A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). 9-16
• 
  François Abel, Christoph Hagleitner, Fabrice Verplanken: Rx Stack Accelerator for 10 GbE Integrated NIC. 17-24

Traffic Generation and Scheduling

• 
  Monia Ghobadi, Geoffrey Salmon, Yashar Ganjali, Martin Labrecque, J. Gregory Steffan: Caliper: Precise and Responsive Traffic Generator. 25-32
• 
  Hans Eberle, Wladek Olesinski: Weighted Differential Scheduler. 33-39

Performance Evaluation

• 
  Samuel K. Gutierrez, Nathan T. Hjelm, Manjunath Gorentla Venkata, Richard L. Graham: Performance Evaluation of Open MPI on Cray XE/XK Systems. 40-47
• 
  Jérôme Vienne, Jitong Chen, Md. Wasi-ur-Rahman, Nusrat S. Islam, Hari Subramoni, Dhabaleswar K. Panda: Performance Analysis and Evaluation of InfiniBand FDR and 40GigE RoCE on HPC and Cloud Computing Systems. 48-55

Routing and Switching

• 
  Zhemin Zhang, Zhiyang Guo, Yuanyuan Yang: Bufferless Routing in Optical Gaussian Macrochip Interconnect. 56-63
• 
  Fredy D. Neeser, Nikolaos Chrysos, Rolf Clauberg, Daniel Crisan, Mitchell Gusat, Cyriel Minkenberg, Kenneth M. Valk, Claude Basso: Occupancy Sampling for Terabit CEE Switches. 64-71

last updated on Tue May 21 02:01:20 2013 by the dblp team
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