Hot Interconnects 2008: Stanford University, CA, USA

On-Chip Interconnects

• Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals:
  A High-Speed Optical Multi-Drop Bus for Computer Interconnections. 3-10
  
• Tushar Krishna, Amit Kumar, Patrick Chiang, Mattan Erez, Li-Shiuan Peh:
  NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication. 11-20
  
• Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic:
  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. 21-30
  
• Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni:
  Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. 31-40
  

Memory Subsystem Interconnects

• John R. Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, Sebastian Turullols:
  Coherency Hub Design for Multi-Node Victoria Falls Server Systems. 43-50
  
• Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng:
  Low Power Passive Equalizer Design for Computer Memory Links. 51-56
  
• Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella:
  OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. 57-63
  

Routing and Performance Evaluation

• Nikos Chrysos, Giorgos Dimitrakopoulos:
  Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation. 67-74
  
• Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata:
  High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections. 75-84
  
• Matthew J. Koop, Wei Huang, Karthik Gopalakrishnan, Dhabaleswar K. Panda:
  Performance Analysis and Evaluation of PCIe 2.0 and Quad-Data Rate InfiniBand. 85-92
  
• Venkata Krishnan:
  Evaluation of an Integrated PCI Express IO Expansion and Clustering Fabric. 93-100
  

Network Processing

• Socrates Demetriades, Michel Hanna, Sangyeun Cho, Rami G. Melhem:
  An Efficient Hardware-Based Multi-hash Scheme for High Speed IP Lookup. 103-110
  
• Miad Faezipour, Mehrdad Nourani:
  Constraint Repetition Inspection for Regular Expression on FPGA. 111-118
  
• Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin, Tatsuya Ishiwata, Kazuyoshi Horie:
  Network Processing on an SPE Core in Cell Broadband Engine. 119-128
  

Industry Talks I

• Huei Pei Kuo, Robert Walmsley, Lennie Kiyama, Michael R. T. Tan, Shih-Yuan Wang:
  Telecentric Optics for Free-Space Optical Link. 131-136
  
• Nitin Godiwala, Jud Leonard, Matthew Reilly:
  A Network Fabric for Scalable Multiprocessor Systems. 137-144
  
• Dawei Wang, Zheng Cao, Xinchun Liu, Ninghui Sun:
  HPP Switch: A Novel High Performance Switch for HPC. 145-153
  

Industry Talks II

• Duncan Roweth, Trevor Jones:
  QsNetIII an Adaptively Routed Network for High Performance Computing. 157-164
  
• Patrick Geoffray, Torsten Hoefler:
  Adaptive Routing Strategies for Modern High Performance Networks. 165-172
  

Industry Leaders Forum: Optical Interconnects

• Ashok V. Krishnamoorthy, Jon Lexau, Xuezhe Zheng, John E. Cunningham, Ron Ho, Ola Tørudbakken:
  Optical Interconnects for Present and Future High-Performance Computing Systems. 175-177
  
• Madeleine Glick:
  Optical Interconnects in Next Generation Data Centers: An End to End View. 178-181
  
• Raymond G. Beausoleil, Jung Ho Ahn, Nathan L. Binkert, Al Davis, David Fattal, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, C. M. Santori, Robert S. Schreiber, S. M. Spillane, Dana Vantrease, Q. Xu:
  A Nanophotonic Interconnect for High-Performance Many-Core Computation. 182-189
  
• Jeffrey A. Kash:
  Leveraging Optical Interconnects in Future Supercomputers and Servers. 190-194
  

Last update Fri May 25 08:15:54 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page