HLDVT 2010: Anaheim, CA, USA

IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010. IEEE 2010

Having Too Many and Too Few Clocks

Bart Vermeulen, Kees Goossens:
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. 1-8
Sumit Ahuja, Wei Zhang, Sandeep K. Shukla:
System level simulation guided approach to improve the efficacy of clock-gating. 9-16
Haiqiong Yao, Hao Zheng, Chris J. Myers:
State space reductions for scalable verification of asynchronous designs. 17-24

O. Sarbishei, Yu Pang, Katarzyna Radecka:
Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. 25-32
Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon:
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. 33-39
Nicola Bombieri, Giuseppe Di Guglielmo, Luigi Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli:
HIFSuite: Tools for HDL code conversion and manipulation. 40-41

Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras:
Quick formal modeling of communication fabrics to enable verification. 42-49
Nicholas Donataccio, Hao Zheng:
An improvement in decomposed reachability analysis for symbolic model checking. 50-57
Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Stefano Soffia, Marco Roveri:
Semi-formal functional verification by EFSM traversing via NuSMV. 58-65

Pranav Ashar:
Clock domain verification challenges and scalable solutions. 66

Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards analyzing functional coverage in SystemC TLM property checking. 67-74
Alper Sen, Magdy S. Abadir:
Coverage metrics for verification of concurrent SystemC designs using mutation testing. 75-81
Ashvin Dsouza:
Static analysis of deadends in SVA constraints. 82-89
Ming Gao, Kwang-Ting Cheng:
A case study of Time-Multiplexed Assertion Checking for post-silicon debugging. 90-96

Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker:
Fast and accurate UML State Chart modeling using TLM⁺ control flow abstraction. 97-102
Samar Abdi:
Automatic generation of host-compiled timed TLMs for high level design. 103-104
Nicola Bombieri, Franco Fummi, Valerio Guarnieri:
Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs. 105-112

Maurizio Caramia, Michele Fabiano, Andrea Miele, Roberto Piazza, Paolo Prinetto:
Automated synthesis of EDACs for FLASH memories with user-selectable correction capability. 113-120
Yogesh S. Mahajan, Sharad Malik:
Utility of transaction-level hardware models in refinement checking. 121-128
Rajiv Bhatia, Eyal Bin, Eitan Marcus, Gil Shurek:
An ontology and constraint based approach to cache preloading. 129-136

Rishiyur S. Nikhil:
ESL flows are enabled by high-level synthesis with universality. 137
John Sanguinetti, Eugene Zhang:
The relationship of code coverage metrics on high-level and RTL code. 138-141
Weiwei Chen, Xu Han, Rainer Dömer:
ESL design and multi-core validation using the System-on-Chip Environment. 142-147

Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten:
Model reduction techniques for the formal verification of hardware dependent software. 148-153
Wolfgang Müller, Marcio F. da S. Oliveira, Henning Zabel, Markus Becker:
Verification of real-time properties for Hardware-dependent Software. 154-159

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