HiPEAC 2010:
Pisa,
Italy
Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell (Eds.):
High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings.
Lecture Notes in Computer Science 5952 Springer 2010, ISBN 978-3-642-11514-1 
Invited Program
- Bob Iannucci:
Embedded Systems as Datacenters.
1
- Roger Espasa:
Larrabee: A Many-Core Intel Architecture for Visual Computing.
2
Architectural Support for Concurrency
- Henry Hoffmann, David Wentzlaff, Anant Agarwal:
Remote Store Programming.
3-17
- John Sartori, Rakesh Kumar:
Low-Overhead, High-Speed Multi-core Barrier Synchronization.
18-34
- Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris C. Kirkham, Ian Watson:
Improving Performance by Reducing Aborts in Hardware Transactional Memory.
35-49
- Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.
50-65
Compilation and Runtime Systems
- Boubacar Diouf, Albert Cohen, Fabrice Rastello, John Cavazos:
Split Register Allocation: Linear Complexity Without the Performance Penalty.
66-80
- Olga Golovanevsky, Alon Dayan, Ayal Zaks, David Edelsohn:
Trace-Based Data Layout Optimizations for Multi-core Processors.
81-95
- Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé:
Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors.
96-110
- Alexander Monakov, Anton Lokhmotov, Arutyun Avetisyan:
Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures.
111-125
Reconfigurable and Customized Architectures
- Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions.
126-140
- Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras:
Accelerating XML Query Matching through Custom Stack Generation on FPGAs.
141-155
- Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf:
An Application-Aware Load Balancing Strategy for Network Processors.
156-170
- Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Yunheung Paek:
Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.
171-185
Multicore Efficiency,
Reliability,
and Power
- Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke:
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors.
186-200
- Yunlian Jiang, Kai Tian, Xipeng Shen:
Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors.
201-215
- Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt:
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
216-231
- Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny:
Performance and Power Aware CMP Thread Allocation Modeling.
232-246
Memory Organization and Optimization
Programming and Analysis of Accelerators
- George Tzenakis, Konstantinos Kapelonis, Michail Alvanos, Konstantinos Koukos, Dimitrios S. Nikolopoulos, Angelos Bilas:
Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor.
307-321
- Roger Ferrer, Vicenç Beltran, Marc González, Xavier Martorell, Eduard Ayguadé:
Analysis of Task Offloading for Accelerators.
322-336
- Pete Cooper, Uwe Dolinsky, Alastair F. Donaldson, Andrew Richards, Colin Riley, George Russell:
Offload - Automating Code Migration to Heterogeneous Multicore Systems.
337-352
- Frédéric de Mesmay, Srinivas Chellappa, Franz Franchetti, Markus Püschel:
Computer Generation of Efficient Software Viterbi Decoders.
353-368
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