High Performance Computing and I/O Systems

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  Keying Wu, P. K. H. Ng, Xing Dong Jia, Richard M. M. Chen, A. M. Layfield: Performance tuning of a multiprocessor sparse matrix equation solver. 4-13
• 
  Ireneusz Karkowski: Architectural synthesis with possibilistic programming. 14-22
• 
  Glenn Jennings: Symbolic incompletely specified functions for correct evaluation in the presence of indeterminate input values. 23-31
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  Dejan Raskovic, Emil Jovanov, Aleksandar Janicijevic, Veljko M. Milutinovic: An implementation of hash based ATM router chip. 32-40
• 
  Catherine H. Gebotys, Robert J. Gebotys: Optimized mapping of video applications to hardware-software for VLSI architectures. 41-48
• 
  Oleg A. Panfilov: Performance analysis of RAID-5 disk arrays. 49-60
• 
  Kuei Yu Wang, Dan C. Marinescu: Correlation of the paging activity of individual node programs in the SPMD execution mode. 61-

Reflective Memory and Distributed Shared Memory Architectures for OLTP

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  Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic: A survey of distributed shared memory systems. 74-84
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  Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde: Reflective-memory multiprocessor. 85-94
• 
  Mark Natale, Mark Baker, Roger Collins, David Wilson, Stephen Lucci, Izidor Gertner: Pentium MPP for OLTP applications. 95-102
• 
  Nicos Vekiarides: Fault-tolerant disk storage and file systems using reflective memory. 103-113
• 
  Mark Russinovich, Zary Segall: Application-transparent checkpointing in Mach 3.O/UX. 114-123
• 
  Greg Schaffer: MPP UNIX enhancements for OLTP applications. 124-133
• 
  Mark Aldred, Ilya Gertner, Stephen McKellar: A distributed lock manager on fault tolerant MPP . 134-136
• 
  Gilberto Arnaiz: Tuning Oracle7 for nCUBE. 137-139
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  Milan Jovanovic, Milo Tomasevic, Veljko M. Milutinovic: A simulation-based comparison of two reflective memory approaches. 140-

Instruction Level Parallelism

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  Instruction Level Parallelism. 151-152
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  Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. 153-162
• 
  John G. Cleary, Murray Pearson, Husam Kinawi: The architecture of an optimistic CPU: the WarpEngine. 163-172
• 
  Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. 173-180
• 
  Thomas Scholz, Michael Schäfers: An improved dynamic register array concept for high-performance RISC processors. 181-190
• 
  Marc Tremblay, Bill Joy, Ken Shin: A three dimensional register file for superscalar processors. 191-201
• 
  Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau: Reducing memory latency using a small software driven array cache. 202-210
• 
  Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu: A study of the effects of compiler-controlled speculation on instruction and data caches. 211-220
• 
  J. Stan Cox, David P. Howell, Thomas M. Conte: Commercializing profile-driven optimization. 221-228
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  Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor: A comparative evaluation of software techniques to hide memory latency. 229

Scalable Shared-Memory Architectures

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  Introduction. 240-241
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  Mårten Björkman, Fredrik Dahlgren, Per Stenström: Using hints to reduce the read miss penalty for flat COMA protocols. 242-251
• 
  Ian Watson, Alasdair Rawsthorne: Decoupled pre-fetching for distributed shared memory. 252-261
• 
  Alexandre E. Eichenberger, Santosh G. Abraham: Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors. 262-271
• 
  Igor Tartalja, Veljko M. Milutinovic: A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors. 272-

Low Energy ILP Processors

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  Thomas D. Burd, Robert W. Brodersen: Energy efficient CMOS microprocessor design. 288-297
• 
  John Bunda, Donald S. Fussell, William C. Athas: Energy-efficient instruction set architecture for CMOS microprocessors. 298-305
• 
  Ching-Long Su, Alvin M. Despain: Cache designs for energy efficiency. 306-315
• 
  Priyadarsan Patra, Donald S. Fussell: Power-efficient delay-insensitive codes for data transmission. 316-323
• 
  Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye: A technique to determine power-efficient, high-performance superscalar processors. 324-333

last updated on Mon May 20 00:18:02 2013 by the dblp team
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