12. ACM Great Lakes Symposium on VLSI 2002: New York, NY, USA
Kanad Ghose, Patrick H. Madden, Vivek De, Peter M. Kogge (Eds.): Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002. ACM 2002 ISBN 1-58113-462-2
Low Power Design
- Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton: Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. 1-6
- Vassilis Paliouras, Alexander Skavantzos, Thanos Stouraitis: Multi-voltage low power convolvers using the polynomial residue number system. 7-11
- Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino: Enhanced clustered voltage scaling for low power. 18-23
Energy and Delay Considerations
- Victor V. Zyuban: Unified architecture level energy-efficiency metric. 24-29
- Ruchir Puri, David S. Kung, Anthony D. Drumm: Fast and accurate wire delay estimation for physical synthesis of large ASICs. 30-36
Testing and Fault-Tolerance
- Paolo Azzoni, Andrea Fedeli, Franco Fummi, Graziano Pravadelli, Umberto Rossi, Franco Toto: An error simulation based approach to measure error coverage of formal properties. 53-58
- Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky: Self-checking sequential circuits with self-healing ability. 71-76
- Dan Zhao, Shambhu J. Upadhyaya, Martin Margala: Minimizing concurrent test time in SoC's by balancing resource usage. 77-82
VLSI Design
- Boris D. Andreev, Eby G. Friedman, Edward L. Titlebaum: Efficient implementation of a complex ±1 multiplier. 83-88
- Tong Zhang, Keshab K. Parhi: On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders. 89-93
VLSI Circuits
- Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. 112-117
- Falah R. Awwad, Mohamed Nekili: Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects. 118-123
- Sungbae Hwang, Jacob A. Abraham: Selective-run built-in self-test using an embedded processor. 124-129
Design Automation
- Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings: Board-level multiterminal net assignment. 130-135
- Timothy W. O'Neil, Edwin Hsing-Mean Sha: Minimizing resources in a repeating schedule for a split-node data-flow graph. 136-141
- John A. Nestor: A new look at hardware maze routing. 142-147
- Qinwei Xu, Pinaki Mazumder: Novel interconnect modeling by using high-order compact finite difference methods. 148-152
- Michiel De Wilde, Dirk Stroobandt, Jan Van Campenhout: AQUASUN: adaptive window query processing in CAD applications for physical design and verification. 153-159
Potpourri
- J. M. Pierre Langlois, Dhamin Al-Khalili: A low power direct digital frequency synthesizer with 60 dBc spectral purity. 166-171
- Rong Lin, Martin Margala: Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. 172-177
- Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. 178-183
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last updated on 2013-06-18T214307 by the dblp team