9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA.
IEEE Computer Society 1999, ISBN 0-7695-0104-4 
@proceedings{DBLP:conf/glvlsi/1999,
title = {9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999,
Ann Arbor, MI, USA},
booktitle = {Great Lakes Symposium on VLSI},
publisher = {IEEE Computer Society},
year = {1999},
isbn = {0-7695-0104-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Testing
- Irith Pomeranz, Sudhakar M. Reddy:
PASTA: Partial Scan to Enhance Test Compaction.
4-7
- Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
On Applying Set Covering Models to Test Set Compaction.
8-11
- Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On Test Generation with A Limited Number of Tests.
12-15
- Spyros Tragoudas, Maria K. Michael:
Functional ATPG for Delay Faults.
16-19
- Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters.
20-23
- Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.
24-
VLSI Design 1
Delay Modeling
VLSI Design 2
Analog and Digital Testing
- Anna Maria Brosa, Joan Figueras:
On Optimizing Test Strategies for Analog Cells.
92-96
- Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang:
Novel Design for Testability of a Mixed-Signal VLSI IC.
97-100
- Ying Wang, Han Ngee Tan:
The Development of Analog SPICE Behavioral Model Based on IBIS Model.
101-
- Mostafa H. Abd-El-Barr, Yanging Xu, Carl McCrosky:
Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits.
388-
- Von-Kyoung Kim, Tom Chen, Mick Tegethoff:
Fault Coverage Estimation for Early Stage of VLSI Design.
105-108
- Bassam Shaer, Sami A. Al-Arian, David L. Landis:
Pseudo-Exhaustive Testing of Sequential Circuits.
109-
Nanoelectronics 1
- James C. Ellenbogen:
Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus.
392-
- David B. Janes, R. P. Andres, E. H. Chen, J. Dicke, V. R. Kolagunta, J. Lauterbach, T. Lee, J. Liu, M. R. Melloch, E. L. Peckham, T. Pletcher, R. Reifenberger, H. J. Ueng, B. L. Walsh, J. M. Woodall, C. P. Kubiak, B. Kasibhatla:
Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic Circuits.
114-117
- Michael T. Niemier, Peter M. Kogge:
Logic in Wire: Using Quantum Dots to Implement a Microprocessor.
118-121
- Árpád Csurgay, Craig S. Lent, Wolfgang Porod:
Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays?
122-
- Stephen Marshall Goodnick, Jonathan P. Bird, David K. Ferry, Allen D. Gunther, Maroun D. Khoury, Michael Kozicki, M. J. Rack, T. J. Thornton, D. Vasileska-Kafedezka:
Transport in Split Gate MOS Quantum Dot Structures.
394-
- T. P. E. Broekaert, B. Brar, F. Morris, A. C. Seabaugh, G. Frazier:
Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain.
123-
Synthesis
Nanoelectronics 2
- Masafumi Yamamoto, Hideaki Matsuzaki, Toshihiro Itoh, Takao Waho, T. Akeyoshi, J. Osaka:
Ultrahigh-Speed Circuits Using Resonant Tunneling Devices.
150-153
- Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto:
A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs.
154-157
- Tetsuya Uemura, Pinaki Mazumder:
Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit.
158-161
- Patrick Fay, Gary H. Bernstein, David H. Chow, J. Schulman, Pinaki Mazumder, W. Williamson, B. K. Gilbert:
Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications.
162-165
- Daniel Berzon, Terry J. Fountain:
A Memory Design in QCAs using the SQUARES Formalism.
166-
Design Issues
- Chia-Pin R. Liu, Jacob A. Abraham:
Transistor Level Synthesis for Static CMOS Combinational Circuits.
172-175
- Carlos Humberto Llanos Quintero, Marius Strum:
SINMEF - A Decomposition Based Synthesis Tool for Large FSMs.
176-179
- Weiwei Li, Zhongwei Xu, Yan Jin:
An Approach for Testing Safety-Critical Software.
180-183
- Travis E. Doom, Anthony S. Wojcik, Moon-Jung Chung:
Design Recovery for Incomplete Combinational Logic.
184-187
- Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi:
Regression-Based Macromodeling for Delay Estimation of Behavioral Components.
188-191
- Stephen A. Blythe, Robert A. Walker:
Efficiently Searching the Optimal Design Space.
192-
VLSI Circuits 1
Short Papers 1
- H.-Ch. Dahmen, Uwe Gläser, Z. Stamenkovic:
Modell Evaluation Using Genetic Manipulation Techniques.
224-225
- Khaled M. Elleithy, E. G. Abd-El-Fattah:
A Genetic Algorithm for Register Allocation.
226-227
- Kanad Chakraborty, Natesan Venkateswaran:
Congestion Mitigation During Placement.
228-229
- John Karro, James P. Cohoon:
A Spiffy Tool for the Simultaneous Placement and Global Routing for Three-Dimensional Field-Programmable Gate Arrays.
230-231
- Sae Hwan Kim, Shiu-Kai Chin:
Formal Verification of Tree-Structured Carry-Lookahead Adders.
232-233
- Samit Chaudhuri, Robert A. Walker:
Bounding Algorithms for Design Space Exploration.
234-235
- Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour:
Digital Neural Processing Unit for Electronic Nose.
236-237
- Xiaohui Wang, Wolfgang Porod:
A Low Power Charge-Recycling CMOS Clock Buffer.
238-239
- Richard F. Hobson, Allan R. Dyck:
A Multiple-Input Single-Phase Clock Flip-Flop Family.
240-241
- Igor Lemberski:
Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.
242-243
- Md. Altaf-Ul-Amin, Zahari Mohamed Darus:
VHDL Design of a Test Processor Based on Mixed-Mode Test Generation.
244-
Physical Design
MEMS
Verification
VLSI Circuits 2
- Amr N. Hafez, Mohamed I. Elmasry:
A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers.
306-309
- Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang:
NMOS Energy Recovery Logic.
310-313
- Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.
314-317
- Lim Chu Aun, S. M. Rezaul Hasan:
An all Digital BiCMOS Phase Lock Loop for VLSI Processors.
318-320
- José Francisco López, Roberto Sarmiento, Antonio Núñez, Kamran Eshraghian, Stefan Lachowicz, Derek Abbott:
Low Power Techniques for Digital GaAs VLSI.
321-324
- Amr G. Wassal, M. Anwarul Hasan:
A VLSI Architecture for ATM Algorithm-Agile Encryption.
325-
Short Papers 2
- Dirk Stroobandt:
On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule.
330-331
- Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang:
Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS.
332-333
- S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin:
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures.
334-335
- Ihn Kim, Craig S. Steele, Jefferey G. Koller:
A Fully Pipelined, 700MBytes/s DES Encryption Core.
386-
- Teruhiko Kamigata, Koso Murakami, Makoto Iwata, Hiroaki Terada:
Proposal of Data-Driven Processor Architecture Qv-K1.
336-337
- Srinivas Katkoori, Ranga Vemuri:
Accurate Resource Estimation Algorithms for Behavioral Synthesis.
338-339
- Von-Kyoung Kim, Tom Chen:
Assessing Defect Coverage of Memory Testing Algorithms.
340-
- Jacob Savir:
Memory Chip BIST Architecture.
384-
- Xiaowei Li, Paul Y. S. Cheung:
Exploiting Test Resource Optimization in Data Path Synthesis for BIST.
342-343
- Christian Pacha, Peter Glösekötter, Karl Goser, U. Auer, Werner Prost, Franz-Josef Tegude:
Resonant Tunneling Transistors for Threshold Logic Circuit Applications.
344-345
- David Crawley:
A Multilevel Cache Memory Architecture for Nanoelectronics.
346-
Low Power
VLSI Circuits 3
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