5. Great Lakes Symposium on VLSI 1995: Buffalo, NY, USA

5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA. IEEE Computer Society 1995

@proceedings{DBLP:conf/glvlsi/1995,
  title     = {5th Great Lakes Symposium on VLSI (GLS-VLSI '95),  March 16-18,
               1995, The State University of New York at Buffalo, USA},
  booktitle = {Great Lakes Symposium on VLSI},
  publisher = {IEEE Computer Society},
  year      = {1995},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Synthesis I

Dimitrios Karayiannis, Spyros Tragoudas:
Uniform area timing-driven circuit implementation. 2-7
Frank Poirot, Gerard Tarroux, Ramine Roane:
Optimization using implicit techniques for industrial designs. 8-14
Uwe Hinsberger, Reiner Kolla:
Optimal technology mapping for single output cells. 14-

Analog VLSI

D. J. Klein, M. L. Manwaring:
A Differential Model Approach To Analog Design Automation. 22-27
Eugenia Penn, Leo N. Schelovanov:
A new approach for modeling and optimization of analog systems. 28-32
Bassem A. Alhalabi, Magdy A. Bayoumi:
A scalable analog architecture for neural networks with on-chip learning and refreshing. 33-

Physical Design I

Michael Sheliga, Edwin Hsing-Mean Sha:
Bus minimization and scheduling of multi-chip systems. 40-45
Joseph L. Ganley, James P. Cohoon:
Thumbnail rectilinear Steiner trees. 46-49
James M. Varanelli, James P. Cohoon:
A two-stage simulated annealing methodology. 50-53
J. T. Mowchenko, Y. Yang:
Optimizing wiring space in slicing floorplans. 54-

Low Power Design

Enrico Macii, Massimo Poncino:
Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. 60-65
Nestoras Tzartzanis, William C. Athas:
Design and analysis of a low-power energy-recovery adder. 66-69
Mircea R. Stan, Wayne P. Burleson:
Coding a terminated bus for low power. 70-73
I. S. Abu-Khater, A. Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan:
Circuit/architecture for low-power high-performance 32-bit adder. 74-

Synthesis II

Chuck Monahan, Forrest Brewer:
Symbolic execution of data paths. 80-85
M. Esen Tuna, Kamlesh Rath, Steven D. Johnson:
Specification and synthesis of bounded indirection. 86-89
Harry Hollander, Bradley S. Carlson, Toby D. Bennett:
Synthesis of SEU-tolerant ASICs using concurrent error correction. 90-93
Jayesh Siddhiwala, Liang-Fang Chao:
Scheduling conditional data-flow graphs with resource sharing. 94-

Verification

Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell:
Automated verification of temporal properties specified as state machines in VHDL. 100-105
Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin:
Partitioning transition relations efficiently and automatically. 106-111
Enrico Macii, Massimo Poncino:
Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions. 112-

Physical Design II

Nikolaos G. Bourbakis, Mohammad Mortazavi:
An efficient building block layout methodology for compact placement. 118-123
Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten:
Performance driven standard-cell placement using the genetic algorithm. 124-127
Jin-Tai Yan:
An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement. 128-131
Ines Peters, Paul Molitor:
Priority driven channel pin assignment. 132-

Architecture and Design I

N. Ranganathan, K. B. Doreswamy:
A systolic algorithm and architecture for image thinning. 138-143
Garth Baulch, David Hemmendinger, Cherrice Traver:
Analyzing and verifying locally clocked circuits with the concurrency workbench. 144-147
Jae-Tack Yoo, Erik Brunvand, Kent F. Smith:
Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. 148-151
Seokjin Kim, Ramalingam Sridhar:
A local clocking approach for self-timed datapath designs. 152-

Synthesis III

Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo:
A soft computing approach to hardware software codesign. 158-163
Stanley Habib, Quan Xu:
Technology mapping algorithms for sequential circuits using look-up table based FPGAS. 164-167
Ali Assi, Bozena Kaminska:
Modeling of communication protocols in VHDL. 168-171
M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward:
Using EDIF for software generation. 172-

Testing

Hon Fung Li, P. N. Lam:
A protocol extraction strategy for control point insertion in design for test of transition signaling circuits. 178-183
Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges:
Statistical estimation of delay fault detectabilities and fault grading. 184-187
Hao Zheng, Kewal K. Saluja, Rajiv Jain:
Test application time reduction for scan based sequential circuits. 188-191
Anne-Lise Courbis, Jean François Santucci:
Pseudo-random behavioral ATPG. 192-

Physical Design III

Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Fast algorithm for performance-oriented Steiner routing. 198-203
Anthony D. Johnson:
On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing. 204-207
Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, A. Sureka:
OPRON: a new approach to planar OTC routing. 208-212
Sanjay Khanna, Shaodi Gao, Krishnaiyan Thulasiraman:
Parallel hierarchical global routing for general cell layout. 212-

Asynchronous Circuits

Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha:
Improving self-timed pipeline ring performance through the addition of buffer loops. 218-223
O. A. Petlin, Stephen B. Furber:
Scan testing of asynchronous sequential circuits. 224-229
Enric Pastor, Jordi Cortadella, Oriol Roig:
A new look at the conditions for the synthesis of speed-independent circuits. 230-

VLSI Education

L. F. Fuller, C. Kraaijenvanger:
Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT. 238-241
Hardy J. Pottinger, Chien-Yuh Lin:
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. 242-245
Robert Pearson:
Linking fabrication and parametric testing to VLSI design courses. 246-249
Wallace B. Leigh:
A personal computer based VLSI design curriculum. 250-

Architecture and Design II

A. Agrawal, A. Raju, S. Varadarajan, Magdy A. Bayoumi:
A scalable shared buffer ATM switch architecture. 256-261
Pong P. Chu:
ATM burst traffic generator. 262-265
W. H. F. J. Körver:
A universal formalization of the effects of threshold voltages for discrete switch-level circuit models. 266-

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