18. FPL 2008: Heidelberg, Germany

Modelling

Encryption Applications

Networks on Chip I

Analysis of Reconfigurability

Image and Video Processing

FPGA Architecture

Dynamic Reconfiguration

Search and Matching Acceleration

Reconfigurable ASIP Design

Compilers for Reconfigurable Architectures

Novel Applications

Reconfigurable Processors

Analysis of Reconfigurability II

Random Number Generation & PLL

Networks on Chip II

Codesign

FPGA Application in High Energy Physics

Reconfigurable Processor Arrays

Tools for FPGA Design

High Performance Computing for Financial and Biological Modelling

SPP1148 booth

Synthesis

Algorithm Acceleration

Optimization

Surveys and Trends

Reconfigurable Architectures

Design Methods and Tools

Applications

Reconfigurable Architectures

Design Methods and Tools

Applications

Reconfigurable Architectures

Design Methods and Tools

Applications

Reconfigurable Architectures

Design Methods and Tools

Applications

Reconfigurable Architectures

Design Methods and Tools

Applications

Surveys, Trends and Education

PhD Forum Presentations