7. FPL 1997: London, UK
Wayne Luk, Peter Y. K. Cheung, Manfred Glesner (Eds.): Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings. Springer 1997 Lecture Notes in Computer Science ISBN 3-540-63465-7
Devices and Architectures
- Julio Faura, Juan Manuel Moreno, Miguel Angel Aguirre Echánove, Phuoc van Duong, Josep Maria Insenser: Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor. 1-10
- Toshiaki Miyazaki, Atsushi Takahara, Masaru Katayama, Takahiro Murooka, Takaki Ichimori, Ken-nosuke Fukami, Akihiro Tsutsui, Kazuhiro Hayashi: CAD-oriented FPGA and dedicated CAD system for telecommunications. 11-20
- Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Paul M. Zavracky: Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. 21-30
- Gordon McGregor, Patrick Lysaght: Extending dynamic circuit switching to meet the challenges of new FPGA architectures. 31-40
- David Robinson, Patrick Lysaght, Gordon McGregor, Hugh Dick: Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs. 41-50
- Tien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch: Implementation of pipelined multipliers on Xilinx FPGAs. 51-60
Devices and Systems
- Igor Kostarnov, Steve Morley, Javed Osmany, Charlie Solomon: A reconfigurable approach to low cost media processing. 79-90
- Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford: Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. 91-100
Reconfiguration 1
- Brian Kahne, Peter M. Athanas: Stream synthesis for a wormhole run-time reconfigurable platform. 101-110
- Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung: Pipeline morphing and virtual pipelines. 111-120
- Barry Rising, Max van Daalen, Peter Burge, John Shawe-Taylor: Parallel Graph colouring using FPGAs. 121-130
- John M. Emmert, Dinesh Bhatia: Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. 141-150
- Jason Leonard, William H. Mangione-Smith: A case study of partially evaluated hardware circuits: Key-specific DES. 151-160
- Rob Payne: Run-time parameterised circuits for the Xilinx XC6200. 161-172
Reconfiguration 2
- Gordon J. Brebner: Automatc identification of swappable logic units in XC6200 circuitry. 173-182
- Patrick Lysaght: Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic. 183-192
- Brad L. Hutchings: Exploiting reconfigurability through domain-specific systems. 193-202
Design Tools
- Vaughn Betz, Jonathan Rose: VPR: A new packing, placement and routing tool for FPGA research. 213-222
- Maurice Kilavuka Inuani, Jonathan Saul: Technology mapping of heterogeneous LUT-based FPGAs. 223-234
- Klaus Feske, Sven Mulka, Manfred Koegst, Günter Elst: Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs. 235-244
- Xiaochun Lin, Erik L. Dagless, Aiguo Lu: Technology mapping of LUT based FPGAs for delay optimisation. 245-254
- S. J. B. Acock, Keith R. Dimond: Automatic mapping of algorithms onto multiple FPGA-SRAM modules. 255-264
- R. Bruce Maunder, Zoran A. Salcic, George G. Coghill: FPLD HDL synthesis employing high-level evolutionary algorithm optimisation. 265-273
- Anton V. Chichkov, Carlos Beltrán Almeida: A hardware/software partitioning algorithm for custom computing machines. 274-283
Custom Computing and Codesign
- Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger: Data scheduling to increase performance of parallel accelerators. 294-303
- Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger: An operating system for custom computing machines based on the Xputer paradigm. 304-313
Signal Processing
- Andreas Dandalis, Viktor K. Prasanna: Fast parallel implementation of DFT using configurable devices. 314-323
- David Greenfield, Caleb Crome, Martin S. Won, Doug Amos: Enhancing fixed point DSP processor performance by adding CPLDs as coprocessing elements. 324-332
- Mark Shand: A case study of algorithm implementation in reconfigurable hardware and software. 333-343
- Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk: A reconfigurable data-localised array for morphological algorithms. 344-353
- T. Mathews, S. G. Gibb, Laurence E. Turner, Peter J. W. Graumann, M. Fattouche: An FPGA implementation of a matched filter detector for spread spectrum communications systems. 364-373
Image and Video Processing
- Ferran Lisa, Faustino Cuadrado, Dolores Rexachs, Jordi Carrabina: A reconfigurable coprocessor for a PCI-based real time computer vision system. 392-399
Sensors, Graphics and other Applications
- C. C. Jong, Y. Y. H. Lam, L. S. Ng: FPGA implementation of a digital IQ demodulator using VHDL. 410-417
- Ian Page: Hardware compilation, configurable platforms and ASICs for self-validating sensors. 418-427
- Satnam Singh, John W. Patterson, Jim Burns, Michael Dales: PostscriptTM rendering with virtual hardware. 428-437
- Ilija Hadzic, Jonathan M. Smith: P4: A platform for FPGA implementation of protocol boosters. 438-447
- Tudor Jebelean: Auto-configurable array for GCD computation. 457-461
- Bernard Laurent, G. Bosco, Gabriele Saucier: Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. 462-471
Controls and Robotics
- Arnaud Tisserand, Martin Dimmler: FPGA implementation of real-time digital controllers using on-line arithmetic. 472-481
- Thomas Hollstein, Andreas Kirschbaum, Manfred Glesner: A prototyping environment for fuzzy controllers. 482-490
- Kazumasa Nukata, Yuichiro Shibata, Hideharu Amano, Yuichiro Anzai: A reconfigurable sensor-data processing system for personal robots. 491-500
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last updated on 2013-06-18T214307 by the dblp team