High-level Design 1

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  Markus Weinhardt: Portable Pipeline Synthesis for FCCMs. 1-13
• 
  Christian Legl, Klaus Eckl, Bernd Wurth: Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play? 14-23

New Software and Hardware Development Tools

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  Wayne Luk, Shaori Guo, Nabeel Shirazi, N. Zhuang: A Framework for Developing Parameterised FPGA Libraries. 24-33
• 
  Toshiaki Miyazaki, Akihiro Tsutsui, Kenji Ishii, Naohisa Ohta: FACT: Co-evaluation Environment for FPGA Architecture and CAD System. 34-43
• 
  Jörn Stohmann, Erich Barke: A Universal CLA Adder Generator for SRAM-Based FPGAs. 44-54
• 
  Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano: An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware. 55-64

Custom Computers

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  Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. 65-76
• 
  Stefan H.-M. Ludwig: The Design of a Coprocessor Board Using Xilinx's XC6200 FPGA - An Experience Report. 77-86
• 
  Doug Smith, Dinesh Bhatia: RACE: Reconfigurable and Adaptive Computing Environment. 87-95
• 
  Chris Dick: Computing 2-D DFTs Using FPGAs. 96-105

High-level Design 2

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  Ulrike Ober, Hans-Jürgen Herpel, Manfred Glesner: CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping. 106-115
• 
  David W. Trainor, Roger Woods: Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays. 116-125
• 
  Carl Ebeling, Darren C. Cronquist, Paul Franklin: RaPiD - Reconfigurable Pipelined Datapath. 126-135

Applications

• 
  Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada: Solving Satisfiability Problems on FPGAs. 136-145
• 
  César Sanz, Laura de Zulueta, Juan M. Meneses: FPGA Implementation of the Block-Matching Algorithm for Motion Estimation in Image Coding. 146-155
• 
  Michael Braun, Jörg Friedrich, Thomas Grün, Josef Lembert: Parallel CRC Computation in FPGAs. 156-165
• 
  Uwe Meyer-Bäse: Coherent Demodulation with FPGAs. 166-175

Hardware/Software Co-Design

• 
  Stephan W. Gehring, Stefan H.-M. Ludwig: The Trianus System and Its Application to Custom Computing. 176-184
• 
  Nigel Lester, Jonathan Saul: Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form. 185-192
• 
  Kalle Tammemäe, Mattias O'Nils, Ahmed Hemani: Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems. 193-199

ASIC Emulators etc.

• 
  Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano: ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. 200-209
• 
  Nikolaj Janzen, Franz J. Rammig: A Slow Motion Engine for the Analysis of FPGA-Based Prototypes. 210-219

Vendor Session

• 
  Alfred Hesener: Implementing Reconfigurable Datapaths in FPGAs for Adaptive Filter Design. 220-229
• 
  Tom Kean, Bernie New, Robert Slous: A Fast Constant Coefficient Multiplier for the XC6200. 230-236
• 
  Albrecht Ditzinger, Ralph Remme: Key Issues for User Acceptance of FPGA Design Tools. 237-241

Industrial Applications and Experiences

• 
  B. L. Combridge, P. S. Cornfield, S. Naunton: Reconfigurable DSP Demonstrators for the Development of Spacecraft Payload Processors. 242-251
• 
  Steve Casselman: Reconfigurable Logic Based Fibre Channel Network Card With Sub 2 Micro-Second Raw Latency. 252-259
• 
  John R. Haddy, David J. Skellern: An Asynchronous Transfer Mode (ATM) Stream Demultiplexer and Switch. 260-269

Reconfiguration Aspects

• 
  Milan Vasilko, Djamel Ait-Boudaoud: Optically Reconfigurable FPGAs: Is this a Future Trend? 270-279
• 
  Zoran A. Salcic, R. Bruce Maunder: CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs. 280-289
• 
  Milan Vasilko, Djamel Ait-Boudaoud: Architectural Synthesis Techniques for Dynamically Reconfigurable Logic. 290-296
• 
  Holger Eggers, Patrick Lysaght, Hugh Dick, Gordon McGregor: Fast Reconfigurable Crossbar Switching in FPGAs. 297-306

CAD User Experiences

• 
  Gulsun Yasar, Julie Devins, Yelena Tsyrkina, Gregg Stadtlander, Eric Millham: Growable FPGA Macro Generator. 307-316
• 
  Jean-Paul Heron, Roger Woods: Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA. 317-326
• 
  Gordon J. Brebner: A Virtual Hardware Operating System for the Xilinx XC6200. 327-336
• 
  Andrej Trost, Roman Kuznar, Andrej Zemva, Baldomir Zajc: An Experimental Programmable Environment for Prototyping Digital Circuits. 337-345
• 
  Michael Gschwind, Christian Mautner: Migration from Schematic-Based Designs to a VHDL Synthesis Environment. 346-355

Miscellaneous

• 
  Alessandro Balboni, Loris Valenti: ASIC Design and FPGA Design: A Unified Design Methodology Applied to Different Technologies. 356-360
• 
  Chris Dick, Fred Harris: FIR Filtering with FPGAs Using Quadrature Sigma-Delta Modulation Encoding. 361-365
• 
  Kang Yi, Chu Shik Jhon: A New FPGA Technology Mapping Approach by Cluster Merging. 366-370
• 
  L. Larsson: An EPLD Based Transient Recorder for Simulation of Video Signal Processing Devices in an VHDL Environment Close to System Level Conditions. 371-375
• 
  Uwe Meyer-Bäse: Convolutional Error Decoding with FPGAs. 376-380
• 
  Branka Medved Rogina, Karolj Skala, Bozidar Vojnovic: Metastability Characteristics Testing for Programmable Logic Design. 381-388
• 
  Kevin Rowley, Colin Lyden: Implementing Sigma Delta Modulator Prototype Designs on an FPGA. 389-393
• 
  José Luis Ruiz, Yago Torroja, José Luis García: Design of a VME Parametrized Library for FPGAs. 394-399
• 
  Guido Schumacher, Bernhard Josko, Gerhard Wagner, Martin Radetzki: Development of a Telephone Answering Machine in a Lab - FPGAs in Education. 400-404
• 
  V. Tchoumatchenko, T. Vassileva, R. Ribas, Alain Guyot: FPGA Design Migration: Some Remarks. 405-409
• 
  Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon: Concurrent Design of Hardware/Software Dedicated Systems. 410-414
• 
  Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx: The Implementation of a Field Programmable Logic Based Co-Processor for the Acceleration of Discrete Event Simulators. 415-424
• 
  Markus Weinhardt: Computing Weight Distributions of Binary Linear Block Codes on a CCM. 425-430

last updated on Sat May 18 04:54:47 2013 by the dblp team
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