4. FPL 1994: Prague, Czech Republic

Testing

• Michael Hermann, Wolfgang Hoffmann:
  Fault Modeling and Test Generation for FPGAs. 1-10
  
• Ricardo de Oliveira Duarte, Michael Nicolaidis:
  A Test Methodology Applied to Cellular Logic Programmable Gate Arrays. 11-22
  

Layout

• Michal Servít, Zdenek Muzikár:
  Integrated Layout Synthesis for FPGAs. 23-33
  
• Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne:
  Influence of Locig Block Layout Architecture on FPGA Performance. 34-44
  
• Ismail Haritaoglu, Cevdet Aykanat:
  A Global Routing Heuristic for FPGAs Based on Mean Field Annealing. 45-56
  
• Kaushik Roy, Sharat Prasad:
  Power Dissipation Driven FPGA Place and Route Under Delay Constraints. 57-65
  

Synthesis Tools

• Amir H. Farrahi, Majid Sarrafzadeh:
  FPGA Technology Mapping for Power Minimization. 66-77
  
• Hans-Jürgen Brand, Dietmar Mueller, Wolfgang Rosenstiel:
  Specification and Synthesis of Complex Arithmetic Operators for FPGAs. 78-88
  
• Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta:
  A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAs. 89-98
  
• A. R. Naseer, M. Balakrishnan, Anshul Kumar:
  An Efficient Technique for Mapping RTL Structures onto FPGAs. 99-110
  

Compilation Research and CAD

• Volker Hamann:
  A Testbench Design Method Suitable for FPGA-Based Prototyping of Reactive Systems. 111-113
  
• Eugene Goldberg, Ludmila Krasilnikova:
  Using Consensusless Covers for Fast Operating on Boolean Functions. 114-116
  
• Tibor Bartos, Norbert Fristacky:
  Formal Verification of Timing Rules in Design Specifications. 117-119
  

Trade-Offs and Experience

• Andrzej Hlawiczka, Jacek Binda:
  Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. 120-122
  
• Jan Lichtermann, Günter Neustädter:
  A High-Speed Rotation Processor. 123-125
  

Innovations and Smart Applications

• P. Gramata, P. Trebaticky, Elena Gramatová:
  The MD5 Message-Digest Algorithm in the XILINX FPGA. 126-128
  
• Barry S. Fagin, Pichet Chintrakulchai:
  A Reprogrammable Processor for Fractal Image Compression. 129-131
  
• Tudor Jebelean:
  Implementing GCD Systolic Arrays on FPGA. 132-134
  
• Roger B. Hughes, Gerry Musgrave:
  Formal CAD Techniques for Safety-Critical FPGA Design and Deployment in Embedded Subsystems. 135-137
  
• T. Saluvere, D. Kerek, Hannu Tenhunen:
  Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAs. 138-140
  
• R. Nguyen, P. Nguyen:
  FPGA Based Reconfigurable Architecture for a Compact Vision System. 141-143
  

FPGA-Based Computer Architectures

• Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
  A New FPGA Architecture for Word-Oriented Datapaths. 144-155
  
• Peter M. Athanas, A. Lynn Abbott:
  Image Processing on a Custom Computing Platform. 156-167
  
• Christian Iseli, Eduardo Sanchez:
  A Superscalar and Reconfigurable Processor. 168-174
  
• Valentina Salapura, Michael Gschwind, Oliver Maischberger:
  A Fast FPGA Implementation of a General Purpose Neuron. 175-182
  

High Level Design

• Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
  Data-Procedural Languages for FPL-based Machines. 183-195
  
• Marc Daumas, Jean-Michel Muller, Jean Vuillemin:
  Implementing On Line Arithmetic on PAM. 196-207
  
• Xiao-yu Chen, Xiao-ping Ling, Hideharu Amano:
  Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware. 208-219
  
• Mat Newman, Wayne Luk, Ian Page:
  Constraint-based Hierarchical Placement of Parallel Programs. 220-229
  

Prototyping and ASIC Emulators

• Tormod Njølstad, Johnny Pihl, Jø Hofstad:
  ZAREPTA: A Zero Lead-Time, All Reconfigurable System for Emulation, Prototyping and Testing of ASICs. 230-239
  
• Richard W. Wieler, Zaifu Zhang, Robert D. McLeod:
  Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator. 240-250
  
• Thomas Benner, Rolf Ernst, Ingo Könenkamp, Ulrich Holtmann, P. Schüler, H.-C. Schaub, N. Serafimov:
  FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis. 251-258
  
• Apostolos Dollas, Brent Ward, J. D. Sterling Babcock:
  FPGA Based Low Cost Generic Reusable Module for the Rapid Prototyping of Subsystems. 259-270
  

Commercial Devices - Prospects and Experience

• Bradly K. Fawcett, Steven H. Kelem:
  FPGA Development Tools: Keeping Pace with Design Complexity. 271-273
  
• Steven H. Kelem:
  Meaningful Benchmarks for Logic Optimization of Table-Lookup FPGAs. 274-276
  
• David C.-L. Lam:
  Educational Use of Field Programmable Gate Arrays. 277-279
  
• Bradly K. Fawcett, Nick Sawyer, Tony Williams:
  HardWire: A Risk-Free FPGA-to-ASIC Migration Path. 280-282
  
• Nigel Toon:
  Reconfigurable Hardware from Programmable Logic Devices. 283-285
  
• Attila Katona, Péter Szolgay:
  On some Limits of XILINX Based Control Logic Implementations. 286-288
  
• Gerhard Cadek, Peter C. Thorwartl, Georg P. Westphal:
  Experiences of Using XBLOX for Implementing a Digital Filter Algorithm. 289-291
  
• Nigel Toon:
  Continuous Interconnect Provides Solution to Density/Performance Trade-Off in Programmable Logic. 292-294
  
• Om P. Agrawal:
  A High Density Complex PLD Family Optimized for Flexibility, Predictability and 100% Routability. 295-297
  
• Patrick Lysaght, David McConnell, Hugh Dick:
  Design Experience with Fine-Grained FPGAs. 298-302
  

New Tools

• Andrew Leaver:
  FPGA Routing Structures from Real Circuits. 303-305
  
• André Klindworth:
  A Tool-Set for Simulating Altera-PLDs Using VHDL. 306-308
  
• John Ant. Hallas, Evaggelinos P. Mariatos, Michael K. Birbas, Alexios N. Birbas, Constantinos E. Goutis:
  A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules. 309-311
  

CCMS and HW/SW Co-Design

• C. P. Cowen, S. Monaghan:
  Performance Characteristics of the Monte-Carlo Clustering Processor (MCCP) - a Field Programmable Logic- based Custom Computing Machine. 321-314
  
• Gerd vom Bögel, Petra Nauber, Jörg Winkler:
  A Design Environment with Emulation of Prototypes for Hardware/Software Systems Using XILINX FPGA. 315-317
  
• Jouni Isoaho, Axel Jantsch, Hannu Tenhunen:
  DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques. 318-320
  
• Jirí Danecek, Alois Pluhácek, Michal Servít:
  The Architecture of a General-Purpose Processor Cell. 321-325
  

Modelers

• Michael Gschwind, Christian Mautner:
  The Design of a Stack-Based Microprocessor. 326-331
  
• Mohamed Akil, Marcelo Alves de Barros:
  Implementation and Performance Evaluation of an Image Pre-Processing Chain on FPGA. 332-334
  
• E. P. Kalosha, Vyacheslav N. Yarmolik, Mark G. Karpovsky:
  Signature Testability of PLA. 335-337
  

Educational Experience

• Ibrahim bin Mat, James M. Noras:
  A FPL Prototyping Package with a C++ Interface for the PC Bus. 338-340
  
• Juan J. Rodríguez-Andina, J. Alvarez, Enrique Mandado:
  Design of Safety Systems Using Field Programmable Gate Arrays. 341-343
  

Novel Architectures and Smart Applications

• J. C. Debize, René J. Glaise:
  A Job Dispatcher-Collector Made of FPGAs for a Centralized Voice server. 344-351
  
• Jo Depreitere, Henk Neefs, Herwig Van Marck, Jan Van Campenhout, Roel Baets, Bart Dhoedt, Hugo Thienpont, Irina Veretennicoff:
  An Optoelectronic 3-D Field Programmable Gate Array. 352-360
  
• Kaushik Roy, Sudip Nag:
  On Channel Architecture and Routability for FPGAs Under Faulty Conditions. 361-372
  
• Tsuyoshi Isshiki, Wayne Wei-Ming Dai:
  Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM). 373-384
  

Applications and Educational Experience

• Stephan W. Gehring, Stefan H.-M. Ludwig, Niklaus Wirth:
  A Laboratory for a Digital Design Course Using FPGAs. 385-396
  
• Uwe Meyer-Bäse, Anke Meyer-Bäse, W. Hilberg:
  COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA. 397-408
  
• Georg J. Kempa, Peter Rieger:
  MARC: A Macintosh NUBUS-Expansion Board Based Reconfigurable Test System for Validating Communication Systems. 409-420
  
• Patrick Lysaght, Jon Stockwood, J. Law, D. Girma:
  Artificial Neural Network Implementation on a Fine-Grained FPGA. 421-432
  

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