6. FPGA 1998: Monterey, CA, USA

• Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance:
  A Novel Predictable Segmented FPGA Routing Architecture. 3-11
  
• Atsushi Takahara, Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Kazuhiro Hayashi, Akihiro Tsutsui, Takaki Ichimori, Ken-nosuke Fukami:
  More Wires and Fewer LUTs: A Design Methodology for FPGAs. 12-19
  
• Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung:
  Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. 20-24
  
• Jason Cong, Yean-Yow Hwang:
  Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. 27-34
  
• Peichen Pan, Chih-Chang Lin:
  A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. 35-42
  
• Mohammed A. S. Khalid, Jonathan Rose:
  A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. 45-54
  
• Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas:
  Managing Pipeline-Reconfigurable FPGAs. 55-64
  
• Scott Hauck:
  Configuration Prefetch for Single Context Reconfigurable Coprocessors. 65-74
  
• Huiqun Liu, Kai Zhu, D. F. Wong:
  Circuit Partitioning with Complex Resource Constraints in FPGAs. 77-84
  
• S. A. Senouci, A. Amoura, Helena Krupnova, Gabriele Saucier:
  Timing Driven Floorplanning on Programmable Hierarchical Targets. 85-92
  
• Lan Zhao, D. M. H. Walker, Fabrizio Lombardi:
  Bridging Fault Detection in FPGA Interconnects Using I_DDQ. 95-104
  
• John Lach, William H. Mangione-Smith, Miodrag Potkonjak:
  Efficiently Supporting Fault-Tolerance in FPGAs. 105-115
  
• Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor:
  Constraints from Hell: How to Tell Makes a Good FPGA (Panel). 117-119
  
• Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek:
  Fast Module Mapping and Placement for Datapaths in FPGAs. 123-132
  
• Stephan W. Gehring, Stefan H.-M. Ludwig:
  Fast Integrated Tools for Circuit Design with FPGAs. 133-139
  
• Jordan S. Swartz, Vaughn Betz, Jonathan Rose:
  A Fast Routability-Driven Router for FPGAs. 140-149
  
• Steven Trimberger:
  Scheduling Designs into a Time-Multiplexed FPGA. 153-160
  
• Douglas Chang, Malgorzata Marek-Sadowska:
  Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. 161-167
  
• Steven J. E. Wilton:
  SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. 171-178
  
• Jason Cong, Songjie Xu:
  Technology Mapping for FPGAs with Embedded Memory Blocks. 179-188
  
• Ray Andraka:
  A Survey of CORDIC Algorithms for FPGA Based Computers. 191-200
  
• Paul Graham, Brent E. Nelson:
  FPGA-Based Sonar Processing. 201-208
  
• John R. Koza, Forrest H. Bennett III, Jeffrey L. Hutchings, Stephen L. Bade, Martin A. Keane, David Andre:
  Evolving Computer Programs Using Rapidly Reconfigurable Field-Programmable Gate Arrays and Genetic Programming. 209-219
  
• Scott Hauck, Matthew M. Hosler, Thomas W. Fry:
  High-Performance Carry Chains for FPGAs. 223-233
  
• James R. Anderson, Siddharth Sheth, Kaushik Roy:
  A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. 234-244
  
• Jason Helge Anderson, Stephen Dean Brown:
  An LPGA with Foldable PLA-style Logic Blocks. 244-252
  
• Karlheinz Weiß, Ronny Kistner, Arno Kunzmann, Wolfgang Rosenstiel:
  Advantages of the XC6000 Architecture for Embedded System Design (Abstract). 255
  
• Paul T. Sasaki:
  A Fast FPGA (FFPGA) Using Active Interconnect (Abstract). 255
  
• Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda:
  A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract). 255
  
• David Jefferson, Srinivas Reddy, Christopher Lane, Ninh Ngo, Wanli Chang, Manuel Mijia, Ketan Zaveri, Cameron McClintock, Richard Cliff:
  A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). 256
  
• Helena Krupnova, B. Behnam, Gabriele Saucier:
  Block and IP Wrapping for Efficient Design on FPGAs (Abstract). 256
  
• Silviu M. S. A. Chiricescu, Mankuan Michael Vai:
  Design of a Three-Dimensional FPGA for Reconfigurable Computing Machines (Abstract). 256
  
• Takenori Kouda, Yahiko Kambayashi:
  FPGA Circuit Optimization Based on Block Integration (Abstract). 257
  
• Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman:
  FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). 257
  
• Jo Depreitere, Herwig Van Marck, Jan Van Campenhout:
  GART: A New, Flexible Placement and Routing Tool for Research on FPGA Architectures (Abstract). 257
  
• Emeka Mosanya, Jean-Michel Puiatti, Eduardo Sanchez:
  Hardware Implementation of Generalized Profile Search on the GENSTROM Machine (Abstract). 258
  
• Xue-Jie Zhang, Kam-Wing Ng, Gilbert H. Young:
  High-Level Synthesis Using Genetic Algorithms for Dynamically Reconfigurable FPGAs (Abstract). 258
  
• Walter B. Ligon III, Greg Monn, S. P. McMillan, Kevin Schoonover, Fred Stivers, Keith D. Underwood:
  Implementation of IEEE Single-Precision Floating-Point Operations on FPGAs (Abstract). 258
  
• Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami:
  Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract). 258
  
• Manuel Jiménez, Chin-Long Wey, Michael A. Shanblatt:
  Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract). 259
  
• Oliver Diessel, Hossam A. ElGindy:
  Partial FPGA Rearrangement by Local Repacking (Abstract). 259
  
• Wai-Kei Mak, D. F. Wong:
  Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). 260
  
• Abdellatif Mtibaa, Mohamed Abid, Rached Tourki:
  Rapid Prototyping of Multi-Recommendation Modem (Abstract). 260
  
• Jeanette F. Arrigo, Kevin J. Page, Paul M. Chau, N. C. Tien:
  Reconfigurable Processing for Robust Navigation and Control (Abstract). 260
  
• Takashi Miyamori, Kunle Olukotun:
  REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract). 261
  
• Jacques-Olivier Haenni, Erik Bruchez, Emeka Mosanya, Eduardo Sanchez:
  RENCO: A Reconfigurable Network Computer (Abstract). 261
  
• Hidehisa Nagano, Takayuki Suyama, Akira Nagoya:
  Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract). 261
  
• Jesus Crespo, Juan Carlos Diaz, Pimitivo Matas:
  FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract). 262
  

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