16. FPGA 2008: Monterey, CA, USA

Workshop

Physical design

Technology mapping

Simulation acceleration

Synthesis at higher-level abstractions

Panel

Architecture tools

Architecture

Reconfigurable computing

Random number generators

Poster session 1: architecture and CAD

Poster session 2: computing with reconfigurable technology

Poster session 3: applications and implementations

maintained by Schloss Dagstuhl LZI at University of Trier