14. FPGA 2006: Monterey, CA, USA

Architecture 1

• Tim Tuan, Sean Kao, Ahmad Arif Rahman, Satyaki Das, Steven Trimberger:
  A 90nm low-power FPGA for battery-powered applications. 3-11
  
• Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert:
  Embedded floating-point units in FPGAs. 12-20
  
• Ian Kuon, Jonathan Rose:
  Measuring the gap between FPGAs and ASICs. 21-30
  

CAD 1

• Jason Cong, Kirill Minkovich:
  Optimality study of logic synthesis for LUT-based FPGAs. 33-40
  
• Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
  Improvements to technology mapping for LUT-based FPGAs. 41-49
  
• Mark Holland, Scott Hauck:
  Improving performance and robustness of domain-specific CPLDs. 50-59
  

Application 1

• Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu:
  Design, implementation, and verification of active cache emulator (ACE). 63-72
  
• Christopher R. Clark, David E. Schimmel:
  Modeling the data-dependent performance of pattern-matching architectures. 73-82
  
• Jianhua Liu, Michael Chang, Chung-Kuan Cheng:
  An iterative division algorithm for FPGAs. 83-89
  

Architecture 2

• Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
  Yield enhancements of design-specific FPGAs. 93-100
  
• Julien Lamoureux, Steven J. E. Wilton:
  FPGA clock network architecture: flexibility vs. area and power. 101-108
  

Will power kill FPGAs?

Emerging Technologies

• Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong:
  Performance benefits of monolithically stacked 3D-FPGA. 113-122
  
• Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon:
  Magnetic tunnelling junction based FPGA. 123-130
  
• Dmitri B. Strukov, Konstantin Likharev:
  A reconfigurable architecture for hybrid CMOS/Nanodevice circuits. 131-140
  

Application 2

• Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis:
  A reconfigurable hardware based embedded scheduler for buffered crossbar switches. 143-149
  
• Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier:
  An adaptive Reed-Solomon errors-and-erasures decoder. 150-158
  
• Norbert Pramstaller, Christian Rechberger, Vincent Rijmen:
  A compact FPGA implementation of the hash function whirlpool. 159-166
  

CAD 2

• Kenneth Eguro, Scott Hauck:
  Armada: timing-driven pipeline-aware routing for FPGAs. 169-178
  
• Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer:
  Combining module selection and resource sharing for efficient FPGA pipeline synthesis. 179-188
  
• Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy:
  Power-aware RAM mapping for FPGA embedded memory blocks. 189-198
  

Application 3

• Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
  Application-specific customization of soft processor microarchitecture. 201-210
  
• Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel:
  Fast and accurate resource estimation of automatically generated custom DFT IP cores. 211-220
  

Architecture

• Yohei Matsumoto, Hanpei Koike, Akira Masaki:
  FPGAs with multidimensional mesh topology. 223
  
• Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
  Evaluation of granularity on threshold voltage control in flex power FPGA. 223
  
• K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis:
  A novel methodology for designing high-performance and low-energy FPGA routing architecture. 224
  
• Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
  Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. 224
  
• Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
  A multilevel hierarchical interconnection structure for FPGA. 225
  
• Garrett S. Rose, Mircea R. Stan:
  A programmable majority logic array using molecular scale electronics. 225
  
• Mohammad Tehranipoor, Reza M. Rad:
  Fine-grained island style architecture for molecular electronic devices. 226
  
• Mohammad Tehranipoor, Reza M. Rad:
  Test and recovery for fine-grained nanoscale architectures. 226
  
• Wenyi Feng, Jonathan W. Greene:
  Post-placement interconnect entropy. 227
  
• Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling:
  A type architecture for hybrid micro-parallel computers. 227
  

CAD

• Youngsun Han, Seokjoong Hwang, Seon Wook Kim:
  Jaguar: a compiler infrastructure for Java reconfigurable computing. 228
  
• Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali:
  Testing embedded RAM modules in SRAM-based FPGAs. 228
  
• Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
  Configuration tools for a new multilevel hierarchical FPGA. 229
  
• Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi:
  Effective clustering technique to optimize routability of outer cluster nets. 229
  
• Rajagopal Subramaniyan, Ian A. Troxel, Alan D. George, Melissa C. Smith:
  Simulative analysis of dynamic scheduling heuristics for reconfigurable computing of parallel applications. 230
  

Applications

• Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner:
  High speed FIR filter implementation using add and shift method. 231
  
• Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama:
  Manifold similarity search of DNA sequences with reconfigurable hardware. 231
  
• Manuel Saldaña, Lesley Shannon, Paul Chow:
  The routability of multiprocessor network topologies in FPGAs. 232
  
• Michael Gilroy, James Irvine, William Berrie:
  FPGA based RAID 6 hardware accelerator. 232
  
• Oliver Sims, James Irvine:
  A real-time implementation of Richardson-Lucy deconvolution. 232
  
• Janardhan Singaraju, John A. Chandy:
  A generic lookup cache architecture for network processing applications. 233
  
• Jike Chong, Chidamber Kulkarni, Gordon J. Brebner:
  Building a flexible and scalable DRAM interface for networking applications on FPGAs. 233
  
• Joshua Noseworthy, Miriam Leeser:
  Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. 233
  
• Nathaniel Couture, Kenneth B. Kent:
  Periodic licensing of FPGA based intellectual property. 234
  
• Ronald Scrofano, Viktor K. Prasanna:
  A Performance model for accelerating scientific applications on reconfigurable computers. 234
  
• Vikas Aggarwal, Alan D. George, K. Clint Slatton:
  Reconfigurable computing with multiscale data fusion for remote sensing. 235
  
• David T. Nguyen, Gokhan Memik, Alok N. Choudhary:
  A reconfigurable architecture for network intrusion detection using principal component analysis. 235
  
• Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito:
  Flexible implementation of genetic algorithms on FPGAs. 236
  
• Milan Tichý, Andy Nisbet, David Gregg:
  GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems. 236
  
• Young H. Cho, James Moscola, John W. Lockwood:
  Context-free-grammar based token tagger in reconfigurable devices. 237
  

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