Kathi Fisler, Moshe Y. Vardi: Bisimulation Minimization in an Automata-Theoretic Verification Framework.
115-132
F. Keith Hanna: Automatic Verification of Mixed-Level Logic Circuits.
133-166
Fen Jin, Henrik Hulgaard, Eduard Cerny: Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints.
167-184
Jürgen Ruf, Thomas Kropf: Using MTBDDs for Compostion and Model Checking of Real-Time Systems.
185-202
Carl-Johan H. Seger: Formal Methods in CAD from an Industrial Perspective (abstract).
203
Nazanin Mansouri, Ranga Vemuri: A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool.
204-221