1. FMCAD 1996:
Palo Alto, California, USA
Kurt Keutzer:
The Need for Formal Methods for Integrated Circuit Design.
1-18
Laurent Arditi:
BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions.
34-48
Harald Rueß:
Hierarchical Verification of Two-Dimensional High-Speed Multiplication in PVS: A Case Study.
79-93
David Cyrluk:
Inverting the Abstraction Mapping: A Methodology for Hardware Verification.
172-186
Natarajan Shankar:
PVS: Combining Specification, Proof Checking, and Model Checking.
257-264
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