16. FCCM 2008: Stanford, Palo Alto, USA

Programming

• David J. Greaves, Satnam Singh:
  Kiwi: Synthesis of FPGA Circuits from Parallel Programs. 3-12
  
• Jonathan Bachrach, Dany Qumsiyeh, Mark Tobenkin:
  Hardware Scripting in Gel. 13-22
  
• John Curreri, Seth Koehler, Brian Holland, Alan D. George:
  Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing. 23-30
  

Network Applications

• Hoang Le, Weirong Jiang, Viktor K. Prasanna:
  A SRAM-based Architecture for Trie-based IP Lookup Using FPGA. 33-42
  
• Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese:
  A Scalable High Throughput Firewall in FPGA. 43-52
  
• Antonis Nikitakis, Ioannis Papaefstathiou:
  A Memory-Efficient FPGA-based Classification Engine. 53-62
  

Reconfiguration

• Shannon Koh, Oliver Diessel:
  The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration. 65-76
  
• Matthew French, Erik K. Anderson, Dong-In Kang:
  Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration. 77-86
  
• Wenyin Fu, Katherine Compton:
  Scheduling Intervals for Reconfigurable Computing. 87-96
  

Discrete Applications

• Saar Drimer, Tim Güneysu, Christof Paar:
  DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs. 99-108
  
• Kimmo U. Järvinen, Jorma O. Skyttä:
  High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves. 109-118
  
• Mary Ellen Fuess, Miriam Leeser, Tim Leonard:
  An FPGA Implementation of Explicit-State Model Checking. 119-126
  

Compilation

• William G. Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer:
  Power-Aware and Branch-Aware Word-Length Optimization. 129-138
  
• Kenneth Eguro, Scott Hauck:
  Simultaneous Retiming and Placement for Pipelined Netlists. 139-148
  
• Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan, Philip Heng Wai Leong:
  Map-reduce as a Programming Model for Custom Computing Machines. 149-159
  

Image Processing

• Jack Coyne, David Cyganski, R. James Duckworth:
  FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography. 163-172
  
• Jeff Chase, Brent E. Nelson, John Bodily, Zhaoyi Wei, Dah-Jye Lee:
  Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study. 173-182
  
• Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, Raj Shekhar:
  Multiobjective Optimization of FPGA-Based Medical Image Registration. 183-192
  

Processor-Based Architectures

• Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan:
  Scaling Soft Processor Systems. 195-205
  
• Michael Butts, Brad Budlong, Paul Wasson, Ed White:
  Reconfigurable Work Farms on a Massively Parallel Processor Array. 206-215
  
• Konstantinos Papadopoulos, Ioannis Papaefstathiou:
  Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor. 216-225
  

High-Performance Computing

• David B. Thomas, Wayne Luk:
  Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. 229-238
  
• David DuBois, Andrew DuBois, Carolyn Connor Davenport, Steve Poole:
  Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer. 239-247
  
• Martin C. Herbordt, Francois Kosie, Josh Model:
  An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular Dynamics. 248-257
  

Posters

• Sven-Ole Voigt, Thomas Teufel:
  Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms. 261-262
  
• Hangpei Tian, Deyuan Gao, Wei Wu, Xiaoya Fan, Zhu Yian:
  Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion. 263-264
  
• Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan:
  ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator. 265-268
  
• Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman:
  An Extensible I/O Subsystem. 269-270
  
• Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi:
  Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding. 271-272
  
• Georgios-Grigorios Mplemenos, Ioannis Papaefstathiou:
  MPLEM: An 80-processor FPGA Based Multiprocessor System. 273-274
  
• Hanyu Liu, Xiaolei Chen, Yajun Ha:
  An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. 275-276
  
• Emilio Castillo, César Pedraza, Javier Castillo, Cristobal Camarero, José Luis Bosque, Rafael Menéndez de Llano, José Ignacio Martínez:
  SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable Hardware. 277-278
  
• Miad Faezipour, Mehrdad Nourani:
  Reconfigurable Constraint Repetition Unit for Regular Expression Matching. 279-280
  
• Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding, Harold W. Carter:
  Fast Multivariate Signature Generation in Hardware: The Case of Rainbow. 281-282
  
• Andrew J. Wong, Warren J. Gross:
  Configurable Flow Models for FPGA Particle Graphics Engines. 283-284
  
• Hayden Kwok-Hay So, Robert W. Brodersen:
  Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH. 285-286
  
• Dirk Koch, Christian Haubelt, Jürgen Teich:
  Efficient Reconfigurable On-Chip Buses for FPGAs. 287-290
  
• Andrew W. H. House, Paul Chow:
  Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. 291-292
  
• Karl Meier, Alessandro Forin:
  Hardware Compilation from Machine Code with M2V. 293-295
  
• David DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor Davenport, Steve Poole:
  An Implementation of the Conjugate Gradient Algorithm on FPGAs. 296-297
  
• Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass:
  FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs. 298-299
  
• Andrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass:
  Reconfigurable Computing Cluster Project: Phase I Brief. 300-301
  
• Karthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George:
  Scalable and Portable Architecture for Probability Density Function Estimation on FPGAs. 302-303
  
• Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen:
  A Hardware Efficient Support Vector Machine Architecture for FPGA. 304-305
  
• Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
  Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. 306-309
  
• Ling Zhuo, Qingbo Wang, Viktor K. Prasanna:
  Matrix Computations on Heterogeneous Reconfigurable Systems. 310-311
  
• Jason Wu, John W. Williams, Neil W. Bergmann:
  System Level Design Methodology for Hybrid Multi-Processor SoC on FPGA. 312-313
  
• François Charot, Christophe Wolinski, Nicolas Fau, François Hamon:
  A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture. 314-315
  
• Sherman Braganza, Miriam Leeser:
  An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware. 316-317
  
• Edward Chen, William A. Gruver, Dorian Sabaz, Lesley Shannon:
  Facilitating Processor-Based DPR Systems for non-DPR Experts. 318-319
  
• Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker:
  Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. 320-321
  

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