11. FCCM 2003: Napa, CA, USA

11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, Proceedings. IEEE Computer Society 2003, ISBN 0-7695-1979-2

@proceedings{DBLP:conf/fccm/2003,
  title     = {11th IEEE Symposium on Field-Programmable Custom Computing Machines
               (FCCM 2003), 8-11 April 2003, Napa, CA, Proceedings},
  booktitle = {FCCM},
  publisher = {IEEE Computer Society},
  year      = {2003},
  isbn      = {0-7695-1979-2},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Applications

Steve Young, Peter Alfke, Colm Fewer, Scott McMillan, Brandon Blodget, Delon Levi:
A High I/O Reconfigurable Crossbar Switch. 3-10
Heather A. Wake, Duncan A. Buell:
Congruential Sieves on a Reconfigurable Computer. 11-18
Apostolos Dollas, Christopher Kachris, Nikolaos G. Bourbakis:
Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm. 19-

Network Security

James Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos:
Implementation of a Content-Scanning Module for an Internet Firewall. 31-38
T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay:
Compiling Policy Descriptions into Reconfigurable Firewall Processors. 39-

Communication Techniques

Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong:
Compact FPGA-based True and Pseudo Random Number Generators. 51-61
Vinay Singh, Ann Root, E. Hemphill, Nabeel Shirazi, James Hwang:
Accelerating Bit Error Rate Testing Using a System Level Design Tool. 62-68
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
A Hardware Gaussian Noise Generator for Channel Code Evaluation. 69-

Arithmetic

George A. Constantinides:
Perturbation Analysis for Word-length Optimization. 81-90
B. R. Lee, Neil Burgess:
Improved Small Multiplier Based Multiplication, Squaring and Division. 91-

Device Architecture

Benjamin A. Levine, Herman Schmit:
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable. 101-110
Kenneth Eguro, Scott Hauck:
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development. 111-120
Hiroto Kagotani, Herman Schmit:
Asynchronous PipeRench: Architecture and Performance Estimations. 121-

Fault Modeling and Recovery

Michael J. Wirthlin, Darrel Eric Johnson, Nathan Rollins, Michael P. Caffrey, Paul S. Graham:
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets. 133-142
Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier:
Adaptive Fault Recovery for Networked Reconfigurable Systems. 143-

Applications

Janette Frigo, David Palmer, Maya Gokhale, Marc Popkin-Paine:
Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware. 155-161
Abdsamad Benkrid, Khaled Benkrid, Danny Crookes:
Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA. 162-172
Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis:
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. 173-

Arithmetic

Jian Liang, Russell Tessier, Oskar Mencer:
Floating Point Unit Generation and Evaluation for FPGAs. 185-194
Xiaojun Wang, Brent E. Nelson:
Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. 195-

Programming Frameworks

Pedro C. Diniz, Joonseok Park:
Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. 207-217
Preston A. Jackson, Brad L. Hutchings, Justin L. Tripp:
Simulation and Synthesis of CSP-based Interprocess Communication. 218-227
K. Scott Hemmert, Justin L. Tripp, Brad L. Hutchings, Preston A. Jackson:
Source Level Debugger for the Sea Cucumber Synthesizing Compiler. 228-

Compilation Techniques

Jingzhao Ou, Seonil Choi, Viktor K. Prasanna:
Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications. 241-250
Anthony L. Slade, Brent E. Nelson, Brad L. Hutchings:
Reconfigurable Computing Application Frameworks. 251-

Posters

Prithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe:
Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. 263-264
Irwin Kennedy:
Fast Reconfiguration Through Difference Compression. 265-266
Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, Philip Heng Wai Leong:
FPGA-based SIMD Processor. 267-268
James P. Durbano, Fernando E. Ortiz, John R. Humphrey, Dennis W. Prather, Mark S. Mirotznik:
Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural Overview. 269-270
Ciaran Toal, Sakir Sezer, Xing Yu:
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. 271-272
Abdsamad Benkrid, Khaled Benkrid, Danny Crookes:
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. 273-275
Andrey Filippov:
Recon .gurable High Resolution Network Camera. 276-277
Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor:
Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. 278-279
S. Belkacemi, Khaled Benkrid, Danny Crookes:
A Logic Based Hardware Development Environment. 280-281
Lesley Shannon, Paul Chow:
Standardizing the Performance Assessment of Reconfigurable Processor Architectures. 282-283
Alex K. Jones, Prithviraj Banerjee:
An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. 284-285
Ranjesh G. Jaganathan, Keith D. Underwood, Ron R. Sass:
A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC. 286-287
Christophe Wolinski, Maya Gokhale, Kevin McCabe:
Fabric-Based Systems: Model, Tools, Applications. 288-289
Sumit Mohanty, Jingzhao Ou, Viktor K. Prasanna:
An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAs. 290-291
Shaomeng Li, Jim Torresen, Oddvar Søråsen:
Exploiting Reconfigurable Hardware for Network Security. 292-293
Kyprianos Papademetriou, Apostolos Dollas, Stamatios N. Sotiropoulos:
A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons. 294-295
K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz:
Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. 296
Joonseok Park, Pedro C. Diniz:
Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. 297-299
Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan:
Linear Placement for Static / Dynamic Reconfiguration in JBits. 300-301
Tim Todman, Wayne Luk:
Real-time Extensions to a C-like Hardware Description Language. 302-304
Kiran Puttegowda, Peter Athanas:
RSA encryption using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing Machine. 305-307
Tim Callahan:
Kernel Formation in Garpcc. 308-

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