8. FCCM 2000: Napa, CA, USA

8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, Proceedings. IEEE Computer Society 2000, ISBN 0-7695-0871-5

Architecture

L. Louis Zhang, Qiang Wang, David M. Lewis:
Design of a VLIW Compute Accelerator on the Transmogrifier-2. 3-12
Mark J. Boyd, Tracy Larrabee:
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems. 13-21
Zhiyuan Li, Katherine Compton, Scott Hauck:
Configuration Caching Management Techniques for Reconfigurable Computing. 22-38

Compilation 1

Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky:
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. 39-48
Maya Gokhale, Janice M. Stone, Jeffrey M. Arnold, Mirek Kalinowski:
Stream-Oriented FPGA Computing in the Streams-C High Level Language. 49-58

Applications 1

Stephen M. Scalera, Mark Falco, Brent E. Nelson:
A Reconfigurable Computing Architecture for Microsensors. 59-67
K. H. Leung, K. W. Ma, W. K. Wong, Philip Heng Wai Leong:
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor. 68-76
Henry Styles, Wayne Luk:
Customizing Graphics Applications: Techniques and Programming Interface. 77-90

Compilation 2

Pedro C. Diniz, Joonseok Park:
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. 91-100
Tsutomu Maruyama, Tsutomu Hoshino:
A C to HDL Compiler for Pipeline Processing on FPGAs. 101-112

Cryptographic Applications

Cameron Patterson:
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm). 113-121
Monk-Ping Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong:
A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA. 122-131
Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim:
An Adaptive Cryptographic Engine for IPSec Architectures. 132-144

Programming Tools

Satnam Singh:
Death of the RLOC? 145-152
Philip James-Roxby, Steven A. Guccione:
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations. 153-164

Fault Tolerance

John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici:
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. 165-174
Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey:
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. 175-184
Steven K. Sinha, Peter Kamarchik, Seth Copen Goldstein:
Tunable Fault Tolerance for Runtime Reconfigurable Architectures. 185-194

Wireless Application

Chris Dick, Fred Harris, Michael Rice:
Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs. 195-204
Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner:
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. 205-216

Applications 2

Benjamin A. Levine, R. Reed Taylor, Herman Schmit:
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware. 217-226
Euripides Sotiriades, Apostolos Dollas, Peter Athanas:
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine. 227-235
Cristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric Chappelier:
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars. 236-248

Applications 3

Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey:
A Reliable LZ Data Compressor on Reconfigurable Coprocessors. 249-258
Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi:
EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding. 259-266
Michael J. Wirthlin, Steve Morrison, Paul Graham, Brian Bray:
Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware. 267-278

Poster Session

Katherine Compton, James Cooley, Stephen Knol, Scott Hauck:
Configuration Relocation and Defragmentation for Reconfigurable Computing. 279-280
Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. 281-282
Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi:
Hardware Accelerator for Subgraph Isomorphism Problems. 283-284
K. Henriss, Peter Rüffer, Rolf Ernst, S. Hasenzahl:
A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios. 285-286
Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley:
Reconfigurable Array Media Processor (RAMP). 287-288
Hamish Fallside, Michael John Sebastian Smith:
Internet Connected FPGAs. 289-290
Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano:
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. 291-294
Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura:
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. 295-296
Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. 297-298
Jinwoo Suh, Dong-In Kang, Stephen P. Crago:
A Communication Scheduling Algorithm for Multi-FPGA Systems. 299-300
L. Levinson, Reinhard Männer, M. Sessler, Harald Simmler:
Preemptive Multitasking on FPGAs. 301-302
Aaron Schneider, Robert McIlhenny, Milos D. Ercegovac:
BigSky-An On-Line Arithmetic Design Tool for FPGAs. 303-304
Paul Graham, Brad L. Hutchings, Brent E. Nelson:
Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings. 305-306
George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple Precision for Resource Minimization. 307-308
Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn:
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. 309-312
Tim Tuan, Miguel Figueroa, Frank Lind, Chucai Zhou, Chris Diorio, John Sahr:
An FPGA-Based Array Processor for an Ionospheric-Imaging Radar. 313-314
Nathaniel D. Daw, Seth Copen Goldstein, Dennis Strelow:
Embedded Compilation for Multimedia Applications. 315-316
Kip Walker, Mihai Budiu, Seth Copen Goldstein:
Interfacing Reconfigurable Logic with a CPU. 317-318
Jonathan E. Scalera, Mark Jones:
A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player. 319-320
Jim Harkin, T. Martin McGinnity, Liam P. Maguire:
Accelerating Embedded Applications using Dynamically Reconfigurable Hardware and Evolutionary Algorithms. 321-322
Maria Imecs, Péter Bikfalvi, Sergiu Nedevschi, József Vásárhelyi:
Implementation of a Configurable Controller for an AC Drive Control: A Case Study. 323-324
Reinhard Männer, M. Sessler, Harald Simmler:
Pattern Recognition and Reconstruction on an FPGA Coprocessor Board. 325-328
Steven Derrien, Sanjay V. Rajopadhye:
FCCMS and the Memory Wall. 329-330
Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh:
A C to Hardware/Software Compiler. 331-332
Markus Weinhardt, Wayne Luk:
Evaluating Hardware Compilation Techniques. 333-334
Philip James-Roxby, Brandon Blodget:
Adapting Constant Multipliers in a Neural Network Implementation. 335-336
Héctor Fabio Restrepo, Ralph Hoffmann, Andrés Pérez-Uribe, Christof Teuscher, Eduardo Sanchez:
A Networked FPGA-Based Hardware Implementation of a Neural Network Application. 337-338
Katsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai:
Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems. 339-340
Tim Courtney, Richard H. Turner, Roger Woods:
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. 341-343
Arran Derbyshire, Wayne Luk:
Combining Serialization and Reconfiguration for Convolver Designs. 344-346

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