5. FCCM 1997: Napa, CA, USA

@proceedings{DBLP:conf/fccm/1997,
  title     = {5th IEEE Symposium on Field-Programmable Custom Computing Machines
               (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA},
  booktitle = {FCCM},
  publisher = {IEEE Computer Society},
  year      = {1997},
  isbn      = {0-8186-8159-4},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Device Architecture

• Norman Margolus:
  An FPGA architecture for DRAM-based systolic computations. 2-11
  
• John R. Hauser, John Wawrzynek:
  Garp: a MIPS processor with a reconfigurable coprocessor. 12-21
  
• Steven Trimberger, Dean Carberry, Anders Johnson, Jennifer Wong:
  A time-multiplexed FPGA. 22-29
  

Communication Applications

• John T. McHenry, Patrick W. Dowd, Frank A. Pellegrino, Todd M. Carrozzi, W. B. Cocks:
  An FPGA-based coprocessor for ATM firewalls. 30-39
  
• Tom McDermott, Philip J. Ryan, Mark Shand, David J. Skellern, Terry Percival, Neil Weste:
  A wireless LAN demodulator in a Pamette: design and experience. 40-46
  

Run Time Reconfiguration

• Herman Schmit:
  Incremental reconfiguration for pipelined applications. 47-55
  
• Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung:
  Compilation tools for run-time reconfigurable designs. 56-65
  
• Jim Burns, Adam Donlin, Jonathan Hogg, Satnam Singh, Mark De Wit:
  A dynamic reconfiguration run-time system. 66-76
  

Architectures for Run Time Reconfiguration

• Gordon J. Brebner:
  The swappable logic unit: a paradigm for virtual hardware. 77-86
  
• Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao:
  The Chimaera reconfigurable functional unit. 87-97
  

Architecture

• Ray Bittner, Peter M. Athanas:
  Computing kernels implemented with a wormhole RTR CCM. 98-105
  
• Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg:
  Mapping applications to the RaPiD configurable architecture. 106-115
  
• W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider:
  Defect tolerance on the Teramac custom computer. 116-124
  

Performance

• Laurent Moll, Mark Shand:
  Systems performance measurement on PCI Pamette. 125-133
  
• Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Bedford Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal:
  The RAW benchmark suite: computation structures for general purpose computing. 134-144
  

Software Tools

• Qiang Wang, David M. Lewis:
  Automated field-programmable compute accelerator design using partial evaluation. 145-154
  
• Roger Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring:
  FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). 155-164
  
• Maya Gokhale, D. Gomersall:
  High level compilation for fine grained FPGAs. 165-174
  

CAD Applications

• Pak K. Chan, Martine D. F. Schlag:
  Acceleration of an FPGA router. 175-181
  
• Miron Abramovici, Premachandran R. Menon:
  Fault simulation on reconfigurable hardware. 182-191
  

Image Processing Applications

• Michael Rencher, Brad L. Hutchings:
  Automated target recognition on SPLASH 2. 192-200
  
• John Woodfill, Brian Von Herzen:
  Real-time stereo vision on the PARTS reconfigurable computer. 201-210
  
• Jack Greenbaum, Michael Baxter:
  Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing. 211-218
  

Arithmetic Applications

• Christof Paar, Martin Rosner:
  Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware. 219-225
  
• Yamin Li, Wanming Chu:
  Implementation of single precision floating point square root on FPGAs. 226-233
  

Poster Papers

• Timothy J. Callahan, John Wawrzynek:
  Datapath-oriented FPGA mapping and placement for configurable computing. 234-235
  
• Steven H. Kelem:
  Mapping a real-time video algorithm to a context-switched FPGA. 236-237
  
• Uwe Tangen, Ludger Schulte, John S. McCaskill:
  A parallel hardware evolvable computer POLYP. 238-239
  
• Glenn H. Chapman, Benoit Dufort:
  Laser defect correction applications to FPGA based custom computers. 240-241
  
• Hyun-Kyu Yun, Aaron Smith, Harvey F. Silverman:
  Speech recognition HMM training on reconfigurable parallel processor. 242-243
  
• Neil W. Bergmann, Yuk Ying Chung, Bernard K. Gunther:
  Efficient implementation of the DCT on custom computers. 244-245
  
• Jason Cong, John Peck:
  On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. 246-248
  

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