Jean Mermet (Ed.):
Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994.
IEEE Computer Society 1994, ISBN 0-89791-685-9
: Extended timing diagrams as a specification language.
Kerry S. Lowe
, P. Glenn Gulak
: A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits.
, Stephen Rochel
: Advanced simulation and modeling techniques for hardware quality verification of digital systems.
, Sharat Prasad
: Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects.
Victor V. Denisenko
: MOS VLSI circuit simulation by hardware accelerator using semi-natural models.
: Design tool encapsulation—all problems solved?
: Test pattern generation hardware motivated by pseudo-exhaustive test techniques.
: An automatically verified generalized multifunction arithmetic pipeline.
: BiTeS: a BDD based test pattern generator for strong robust path delay faults.
Chris J. Rousse
, Alison J. Carter
: The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithm.
: A portable and extendible testbed for distributed logic simulation.
, J. Schrage
, M. Vogt
: Fast simulation method for the detection of reflection - and crosstalk effects during the design of complex printed circuit boards.
, Werner John
: Design support of printed circuit boards concerning radiation and irradiation effects (EMI): using an extended EMC-Workbench.
: A macro-cell global router based on two genetic algorithms.
: (V)HDL-based verification of heterogeneous synchronous/asynchronous systems.
: Petri nets as intermediate representation between VHDL and symbolic transition systems.
: Automotive databus simulation using VHDL.
: Rapid prototyping for DSP circuits using high level design tools.