Gordon Adshead , Jochen A. G. Jess (Eds.):
European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990.
IEEE Computer Society 1990, ISBN 0-8186-2024-2 Tools for testing
export record as
dblp key:
conf/eurodac/ZimmermannG90 export record as
dblp key:
conf/eurodac/HodgsonTHI90 export record as
dblp key:
conf/eurodac/HellebrandW90 export record as
dblp key:
Databases and frameworks
export record as
dblp key:
conf/eurodac/KathoferFNPQRS90 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Formal verification
export record as
dblp key:
Ranga Vemuri :
On the notion of the normal form register-level structures and its applications in design-space exploration.
46-51
export record as
dblp key:
conf/eurodac/Collavizza90 Hélène Collavizza :
Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level.
52-56
export record as
dblp key:
export record as
dblp key:
Scheduling and allocation I
export record as
dblp key:
conf/eurodac/DelaruelleMMN90 export record as
dblp key:
Werner Grass :
A branch-and-bound method for optimal transformation of data flow graphs for observing hardware constraints.
73-77
export record as
dblp key:
Neerav Berry ,
Barry M. Pangrle :
SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system.
78-82
export record as
dblp key:
Simulation languages
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/TikkanenLK90
Cell generators
export record as
dblp key:
Akhilesh Tyagi :
An algebraic model for design space with applications to function module generation.
114-118
export record as
dblp key:
conf/eurodac/LefebvreCM90 export record as
dblp key:
export record as
dblp key:
Scheduling and allocation II
export record as
dblp key:
export record as
dblp key:
L. Stok :
Interconnect optimisation during data path allocation.
141-145
export record as
dblp key:
Peter Marwedel :
Matching system and component behaviour in MIMOLA synthesis tools.
146-156
export record as
dblp key:
conf/eurodac/CamposanoB90
Description of design systems and methodologies
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/BeckerBHKKMOPS90 export record as
dblp key:
Jung-Gen Wu :
Automatic knowledge acquisition in a digital circuit design system.
180-184
Compaction and circuit packing
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Combinational logic design optimization
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/BerkelaarJ90 export record as
dblp key:
conf/eurodac/Diaz-OlavarrietaZ90
Simulation I
export record as
dblp key:
D. Patrick ,
C. Lyden :
An event-driven transient simulation algorithm for MOS and bipolar circuits.
230-234
export record as
dblp key:
conf/eurodac/StiphoutEB90 export record as
dblp key:
R. A. Cottrell :
Event-driven behavioural simulation of analogue transfer functions.
240-243
export record as
dblp key:
Floorplanning
export record as
dblp key:
conf/eurodac/MassonBEWCZ90 export record as
dblp key:
conf/eurodac/YonezawaNETH90 export record as
dblp key:
conf/eurodac/McCullenTDL90 export record as
dblp key:
High level synthesis systems
export record as
dblp key:
conf/eurodac/LanneerCGPMM90 export record as
dblp key:
export record as
dblp key:
Simulation II
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/EijndhovenSB90
Placement
export record as
dblp key:
export record as
dblp key:
conf/eurodac/GarbersKPSS90 export record as
dblp key:
export record as
dblp key:
conf/eurodac/HuentemannB90
Delay and CMOS testing
export record as
dblp key:
conf/eurodac/PramanickR90 export record as
dblp key:
export record as
dblp key:
F. Darlay ,
B. Courtois :
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks.
344-349
export record as
dblp key:
Niraj K. Jha ,
Qiao Tong :
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring.
350-354
Databases and datastructuring
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/DrescherMS90 export record as
dblp key:
Physical verification and simulation
export record as
dblp key:
W. Meier :
Hierarchical layout verification for submicron designs.
382-386
export record as
dblp key:
conf/eurodac/MarazziniST90 export record as
dblp key:
export record as
dblp key:
Low-level fault modelling and test generation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/TeixeiraTAGGC90 export record as
dblp key:
conf/eurodac/GruningMDO90
Selected topics in CAD systems
export record as
dblp key:
export record as
dblp key:
F. Theeuwen :
Logic optimization on a concurrent processing computer.
429-433
export record as
dblp key:
D. F. Burrows :
The use of computer-aided software engineering technology in systems and software design.
434-438
export record as
dblp key:
conf/eurodac/HartleyWHDC90
Routing
export record as
dblp key:
conf/eurodac/SrinivasanK90 export record as
dblp key:
Bryan Preas :
Channel routing with non-terminal doglegs.
451-458
export record as
dblp key:
export record as
dblp key:
Test pattern generation and fault simulation
export record as
dblp key:
conf/eurodac/CamuratiLPR90 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Christian Jay :
Experience in functional-level test generation and fault coverage in a silicon compiler.
485-490
Procedural interfaces
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Bruno Poterie :
Storage mechanism for VHDL intermediate form.
506-510
Timing analysis and verification
export record as
dblp key:
export record as
dblp key:
conf/eurodac/JohannesDCM90 export record as
dblp key:
conf/eurodac/Tjarnstrom90 Robert Tjärnström :
Automatic generation of timing specifications for CMOS transistor subnetworks.
524-528
export record as
dblp key:
conf/eurodac/DeschachtPRA90
Finit state machine synthesis I
export record as
dblp key:
Lech Józwiak :
Efficent suboptimal state assignment for large sequential machines.
536-541
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/AvedilloQH90
Simulation modelling
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Physical design optimization
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/HinsbergerK90 export record as
dblp key:
Reiner Kolla :
A dynamic programming approach to the power supply net sizing problem.
600-604
export record as
dblp key:
conf/eurodac/BondonoJHCB90
Finite state machine synthesis - II
export record as
dblp key:
export record as
dblp key:
Verification and PLA testing
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/eurodac/Krasniewski90
Novel approaches in placement
export record as
dblp key:
conf/eurodac/CavigliaBCGR90 export record as
dblp key:
M. Razaz ,
J. Gan :
Fuzzy set based initial placement for IC layout.
655-659
export record as
dblp key:
conf/eurodac/ShahookarM90 export record as
dblp key:
data released under the ODC-BY 1.0 license
