ETS 2011: Trondheim, Norway

ETS'10 Best Paper

• Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
  Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. 1-6
  

Power Switches

• S. Saqib Khursheed, Sheng Yang, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn:
  Improved DFT for Testing Power Switches. 7-12
  
• Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
  Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. 13-18
  

Security

• Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
  Scan Attacks and Countermeasures in Presence of Scan Response Compactors. 19-24
  

Converter Testing

• Esa Korhonen, Juha Kostamovaara:
  Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs. 25-32
  
• S. Kook, A. Banerjee, Abhijit Chatterjee:
  Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation. 33-38
  

3D Technology

• Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai:
  A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. 39-44
  
• Mottaqiallah Taouil, Said Hamdioui:
  Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories. 45-50
  
• Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
  DfT Architecture for 3D-SICs with Multiple Towers. 51-56
  

Emerging Technologies

• Aritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee:
  Power Aware Post-manufacture Tuning of Analog Nanocircuits. 57-62
  
• Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes:
  Tomographic Testing and Validation of Probabilistic Circuits. 63-68
  
• Masoud Zamani, Navid Farazmand, Mehdi Baradaran Tahoori:
  Fault Masking and Diagnosis in Reversible Circuits. 69-74
  

Mixed-Signal and RF Test

• Afsaneh Nassery, Sule Ozev, Marian Verhelst, Mustapha Slamani:
  Extraction of EVM from Transmitter System Parameters. 75-80
  
• Stephen K. Sunter, Aubin Roy:
  A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution. 81-86
  

Dependability

• Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris:
  AVF Analysis Acceleration via Hierarchical Fault Pruning. 87-92
  
• Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh:
  Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. 93-98
  

Test Data Compression, Compaction, and Diagnosis

• Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
  Reduced ATE Interface for High Test Data Compression. 99-104
  
• Ozgur Sinanoglu:
  Toggle-Based Masking Scheme for Clustered Unknown Response Bits. 105-110
  
• Alejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein:
  Structural In-Field Diagnosis for Random Logic Circuits. 111-116
  

Advances in Test

• Nicola Bombieri, Franco Fummi, Valerio Guarnieri:
  Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction. 117-122
  
• Anelise Kologeski, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt:
  Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links. 123-128
  
• Alexander Finder, André Sülflow, Görschwin Fey:
  Latency Analysis for Sequential Circuits. 129-134
  

Contactless and Memory Testing

• Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo, L. Perilli, Roberto Cardu, Eleonora Franchi, C. Gozzi, F. Maggioni:
  Input/Output Pad for Direct Contact and Contactless Testing. 135-140
  

ATPG 1

• Stelios Neophytou, Kyriakos Christou, Maria K. Michael:
  An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration. 141-146
  
• Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara:
  Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. 147-152
  
• Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda:
  A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. 153-158
  

Analog Production Test

• Shaji Krishnan, Hans G. Kerkhoff:
  A Robust Metric for Screening Outliers from Analogue Product Manufacturing Tests Responses. 159-164
  
• Ender Yilmaz, Sule Ozev:
  Fast and Accurate DPPM Computation Using Model Based Filtering. 165-170
  

Post-silicon Debug

• Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita:
  Optimization of Assertion Placement in Time-Constrained Embedded Systems. 171-176
  

ATPG 2

• Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor:
  Critical Fault-Based Pattern Generation for Screening SDDs. 177-182
  

Diagnosis

• Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich:
  Structural Test for Graceful Degradation of NoC Switches. 183-188
  
• Irith Pomeranz:
  On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests. 189-194
  
• Hongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty:
  Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures. 195-200
  

Posters

• H. C. M. Bossers, Johann Hurink, Gerard J. M. Smit:
  Online Univariate Outlier Detection in Final Test: A Robust Rolling Horizon Approach. 201
  
• Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Rick Wong, Shi-Jie Wen:
  Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS. 202
  
• Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara:
  F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. 203
  
• Dongsoo Lee, Kaushik Roy:
  Viterbi-Based Efficient Test Data Compression. 204
  
• Sandra Irobi, Zaid Al-Ars, Said Hamdioui:
  Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs. 205
  
• Ioannis Voyiatzis, Costas Efstathiou, H. Antonopoulou:
  A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture. 206
  
• Uros Legat, Anton Biasizzo, Franc Novak:
  FPGA Soft Error Recovery Mechanism with Small Hardware Overhead. 207
  
• Michael Nicolaidis, Vladimir Pasca, Lorena Anghel:
  I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems. 208
  
• Dhiego Silva, K. Stangherlin, Leticia Maria Veiras Bolzani, Fabian Vargas:
  A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems. 209
  
• Min Li, Michael S. Hsiao:
  High-Performance Diagnostic Fault Simulation on GPUs. 210
  
• Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar:
  Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. 211
  
• Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini:
  A Low-Cost Emulation System for Fast Co-verification and Debug. 212
  
• Alessandro Cilardo, Carmelo Lofiego, Antonino Mazzeo, Nicola Mazzocca:
  Revisiting Application-Dependent Test for FPGA Devices. 213
  
• Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
  Temperature-Variation-Aware Test Pattern Optimization. 214
  
• Ramachandran Venkatasubramanian, Doohwang Chang, Sule Ozev:
  Analysis and Mitigation of Electromigration in RF Circuits: An LNA Case Study. 215
  
• Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
  Enhancement of Clock Delay Faults Testing. 216
  
• Yukiya Miura:
  Dual Edge Triggered Flip-Flops for Noise Aware Design. 217
  
• Feng Yuan, Xiao Liu, Qiang Xu:
  On High-Quality Test Pattern Selection and Manipulation. 218
  

Embedded Tutorial

• Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell:
  Towards Variation-Aware Test Methods. 219-225
  

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