ETS 2009: Sevilla, Spain

Plenary Presentations

• Janusz Rajski:
  We Have Got Compression, What Next?
  
• Christian Landrault:
  Something I Always Wanted to Know About Test, But Was Afraid to Ask.
  

Internal Testing of Mixed-Signal Cores

• S. Kook, Vishwanath Natarajan, Abhijit Chatterjee, Shalabh Goyal, Le Jin:
  Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation. 3-8
  

Debug and Validation

• Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai:
  Speed-Path Debug Using At-Speed Scan Test Patterns. 11-16
  
• Ho Fai Ko, Nicola Nicolici:
  Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. 17-22
  

Power Issues during Test

• Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal:
  On Minimization of Peak Power for Scan Circuit during Test. 25-30
  

Selt-Test and Test Throughput

• Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar:
  Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. 33-38
  
• Frank-Uwe Faber, Matthias Beck, Markus Rudack, Olivier Barondeau, Thomas Rabenalt, Michael Gössel, Andreas Leininger:
  Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment. 39-44
  
• Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud:
  Algorithms for ADC Multi-site Test with Digital Input Stimulus. 45-50
  

On-Line Testing

• Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich:
  Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead. 53-58
  

Advanced Testing of Memories, Power Transistors and Microfluidic Systems

• Olivier Ginez, Jean Michel Portal, Ch. Muller:
  Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. 61-66
  
• Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner:
  Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications. 67-72
  
• Qais Al-Gayem, Hongyuan Liu, Andrew Richardson, Nick Burd:
  Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems. 73-78
  

Recent Advances in ATPG

• Stephan Eggersglüß, Rolf Drechsler:
  Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. 81-86
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. 87-92
  
• Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda:
  Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. 93-98
  

Advanced External Testing of Mixed-Signals Cores

• Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev:
  Defect Filter for Alternate RF Test. 101-106
  
• Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
  Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. 107-112
  

Diagnosis and Dependability Analysis

• Mohammed Ashfaq Shukoor, Vishwani D. Agrawal:
  A Two Phase Approach for Minimal Diagnostic Test Set Generation. 115-120
  
• Yasser Sedaghat, Seyed Ghassem Miremadi:
  Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers. 121-126
  

Impact of Nanometer Technologies in the Testing Methodology

• Kihyuk Han, Joonsung Park, Jae Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh:
  Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. 129-134
  
• Josep Rius, Luis Elvira Villagra, Maurice Meijer:
  A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits. 135-140
  

DfT and Embedded Test

• Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
  Partial Scan Approach for Secret Information Protection. 143-148
  
• Thomas Rabenalt, Michael Gössel, Andreas Leininger:
  Masking of X-values by Use of a Hierarchically Configurable Register. 149-154
  
• Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich:
  Test Encoding for Extreme Response Compaction. 155-160
  

ETS'08 Best Paper

• Rajeshwary Tayade, Jacob A. Abraham:
  Critical Path Selection for Delay Test Considering Coupling Noise. 163-168
  

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