ETS 2007: Freiburg, Germany

Plenary Presentations

• Rene Segers:
  If It's All about Yield, Why Talk about Testing? 3
  
• Ben Bennetts:
  Electronics Design-for-Test: Past, Present and Future. 4
  

Fault and Defect Diagnosis

• Stefan Holst, Hans-Joachim Wunderlich:
  Adaptive Debug and Diagnosis without Fault Dictionaries. 7-12
  
• Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
  DERRIC: A Tool for Unified Logic Diagnosis. 13-20
  

Mixed Signal DFT and Test

• Erik Schüler, Marcelo Negreiros, Pascal Nouet, Luigi Carro:
  A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter. 21-28
  

NoC Testing

• Jaan Raik, Raimund Ubar, Vineeth Govind:
  Test Configurations for Diagnosing Faulty Links in NoC Switches. 29-34
  
• Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
  Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. 35-42
  

Advances in RF Test

• Ivo Koren, Frank Demmerle, Roland May, Martin Kaibel, Sebastian Sattler:
  FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests. 43-48
  
• Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
  Digital Generation of Signals for Low Cost RF BIST. 49-54
  
• Shaji Krishnan, Rene Jonker, Leon van de Logt:
  Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives. 55-62
  

Diagnosis and Debug

• Tao Xu, Krishnendu Chakrabarty:
  Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips. 63-68
  
• Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek:
  Communication-Centric SoC Debug Using Transactions. 69-76
  

Simulation and Verification

• Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
  Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. 77-84
  

Memory Test

• Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero:
  PPM Reduction on Embedded Memories in System on Chip. 85-90
  
• Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich:
  An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. 91-96
  
• Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
  Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. 97-104
  

On-Line Testing and Self-Test

• Norbert Dumas, Zhou Xu, Kostas Georgopoulos, R. John T. Bunyan, Andrew Richardson:
  A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus. 105-110
  
• Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
  Selecting Power-Optimal SBST Routines for On-Line Processor Testing. 111-116
  
• Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara:
  Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors. 117-124
  

Fault Grading and Test Quality

• Zhanglei Wang, Krishnendu Chakrabarty, Michael Bienek:
  A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression. 125-130
  
• Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
  Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. 131-136
  
• Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel:
  Computation and Application of Absolute Dominators in Industrial Designs. 137-144
  

Diagnosis and Yield Improvement

• Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware:
  Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. 145-150
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Diagnostic Test Generation Based on Subsets of Faults. 151-158
  

Single Event Upsets

• Luca Sterpone, Massimo Violante:
  Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. 159-164
  
• Carlos Arthur Lang Lisbôa, Marcelo Ienczczak Erigson, Luigi Carro:
  System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies. 165-172
  

Delay and Performance Test

• Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab:
  Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. 173-178
  
• Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
  On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. 179-184
  
• Stephen K. Sunter, Aubin Roy:
  Purely Digital BIST for Any PLL or DLL. 185-192
  

Embedded Tutorials

• Philippe Cauvet, Serge Bernard, Michel Renovell:
  System-in-Package, a Combination of Challenges and Solutions. 193-199
  
• Klaus Luther:
  Embedded Tutorial: IC Test Cost Benchmarking. 200
  
• Peter Maxwell:
  Wafer Level Reliability Screens. 201
  
• Nicola Nicolici, Xiaoqing Wen:
  Embedded Tutorial on Low Power Test. 202-210
  

ETS06 Best Paper

• Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
  "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. 211-216
  

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