Keynotes

• 
  Steven A. Guccione: Multicore Devices: A New Generation of Reconfigurable Architectures. 3-11

Invited Talks and Papers

• 
  Jerry L. Trahan: Reconfigurable Mesh Techniques and Applications. 15-28
• 
  Parag K. Lala: On FPGA Design with Self-checking and Fault Tolerance Capability. 29-34
• 
  Marco Platzner, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, Alexander Warkentin: The GOmputer: Accelerating GO with FPGAs. 35-45

Panel and Workshop

• 
  David L. Andrews, Jason Agron: Modeling Abstractions for Next Generation Reconfigurable Computing. 49-56
• 
  Brent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn Bohner: Design Productivity for Configurable Computing. 57-66
• 
  Bernard Pottier: FPGAs or Distributed Systems? 67-75
• 
  John Watson, Steven H. Kelem, Brian Box, Joseph Hassoun, Stephen Wasson, Bob Plunkett, Chris Phillips: A New Tact in Reconfigurable Computing Research. 76-78
• 
  Chris Eddington: Industrial Workshop - Architectural Synthesis for Reconfigurable Computing. 79

Adaptive and Dynamically Reconfigurable Systems

• 
  Enno Lübbers, Marco Platzner: Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. 83-89
• 
  Georges Adouko, François Charot, Christophe Wolinski: A New High Performance Multi Gigabit String Matching Engine. 90-96
• 
  Kehuai Wu, Esben Rosenlund Hansen, Jan Madsen: Towards Understanding and Managing the Dynamic Behavior of Run-Time Reconfigurable Architectures. 97-103
• 
  Erik K. Anderson, Matthew French, Dong-In Kang: System on a Programmable Chip Adaptation Through Active Partial Reconfiguration. 104-110
• 
  Edgar Ferrer, Dorothy Bollman: A New Efficient Architecture for Univariate Polynomial Interpolation Over GF(2^m). 111-115
• 
  Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu: A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. 116-121
• 
  Chris Conger, Ann Gordon-Ross, Alan D. George: Design Framework for Partial Run-Time FPGA Reconfiguration. 122-128
• 
  Joseph Hassoun, Steve Kelemjoseph, Brian Box, Stephen Wasson, Bob Plunkett, Chris Phillips: Elemental Computing for High Reliability. 129-135

Reconfigurable Computing for Space Based Applications

• 
  Heather Quinn, Paul S. Graham, Keith Morgan, Jim Krone, Michael P. Caffrey, Michael J. Wirthlin: An Introduction to Radiation-Induced Failure Modes and Related Mitigation Methods For Xilinx SRAM FPGAs. 139-145
• 
  Adam Jacobs, Grzegorz Cieslewski, Casey Reardon, Alan D. George: Multiparadigm Computing for Space-Based Synthetic Aperture Radar. 146-152
• 
  Brian H. Pratt, Michael P. Caffrey, Derrick Gibelyou, Paul S. Graham, Keith Morgan, Michael J. Wirthlin: TMR with More Frequent Voting for Improved FPGA Reliability. 153-158
• 
  Sandeep K. Venishetti, Ali Akoglu: Highly Parallel FPGA Based IEEE-754 Compliant Double-Precision Floating-Point Division. 159-165

Reconfigurable System Design Tools and Languages

• 
  Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan: SystemC-based Custom Reconfigurable Cores for Wireless Applications. 169-175
• 
  Wim Vanderbauwhede: A Formal Semantics for Control and Data flow in the Gannet Service-based System-on-Chip Architecture. 176-183
• 
  Wesley Holland, Yoginder S. Dandass: Optimizing Pipelining in HDL Generated Automatically from C Source Codes. 184-190
• 
  Miaoqing Huang, Ivan Gonzalez, Sergio López-Buedo, Tarek A. El-Ghazawi: A Framework to Improve IP Portability on Reconfigurable Computers. 191-197

Multi-Context Devices and Applications

• 
  Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. 201-207
• 
  Vu Manh Tuan, Hideharu Amano: A Method for Capturing State Data on Dynamically Reconfigurable Processors. 208-214
• 
  Masaru Kato, Yohei Hasegawa, Hideharu Amano: Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. 215-221
• 
  Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe: MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. 222-228

Applications of Reconfigurable Systems

• 
  Kuei-Tsung Shih, Arjun Balachandran, Karthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George: Fast Real-Time LIDAR Processing on FPGAs. 231-237
• 
  Zachary K. Baker, Justin L. Tripp: Gradient Run-length Data Compression for Real-time Airborne Image Processing. 238-244
• 
  Tobias Schumacher, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, Marco Platzner: A Hardware Accelerator for k-th Nearest Neighbor Thinning. 245-251
• 
  Abdel Ejnioui, Paul Bao: A Parallel Array to Accelerate GFA Modeling in Video Coding. 252-258
• 
  Scott Lloyd, Quinn Snell: Qnet: A Modular Architecture for Reconfigurable Computing. 259-265

Short Papers

• 
  Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara: Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration. 269-272
• 
  Adarsha Sreeramareddy, Jeff G. Josiah, Ali Akoglu: SCARS: Scalable Self-Configurable Architecture for Reusable Space Systems. 273-276
• 
  Gary Block, Paula Pingree, Yungling Lou: Selection and Use of Programmable Logic in Flight Applications. 277-280
• 
  Robert Collier Barnes, Aravind Dasu: Hardware/Software Co-designed Extended Kalman Filter on an FPGA. 281-284
• 
  Arjun K. Pai, Khaled Benkrid: Multi-Criteria Optimization and Performance Measurement of Domain-Specific Reconfigurable Architectures Targeting Image and Video Processing Applications. 285-288
• 
  Mao Nakajima, Minoru Watanabe: A 770ns Holographic Reconfiguration of a Four-Context DORGA. 289-292
• 
  Qiwei Zhang, Karel H. G. Walters, André B. J. Kokkeler, Gerard J. M. Smit: Dynamically Reconfigurable FFTs for Cognitive Radio on a Multiprocessor Platform. 293-297
• 
  Andrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci: High Performance Double Precision Reduction Circuit Implementation in FPGA. 298-301

Posters

• 
  Mariam Hoseini, Chao You, Mark Pavicic: A Cellular Automata ASIC for Conformal Computing. 305-306
• 
  Angel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos: Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. 307-308
• 
  Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama: Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. 309-310
• 
  Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi: FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. 311-312
• 
  Yidong Liu, Srinivasan Santhanam, Jooheung Lee: Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study. 313-314

Late Papers

• 
  Laura Sánchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo: FPGA Resource Management Using Internal RAM as Aata Cache. 317-318
• 
  Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo: Resource Management for Hw Multitasking in Three Dimensional FPGAs. 319-320
• 
  Victor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III: The Viability of Cellular Automata Architectures for General Purpose Computing. 321-333
• 
  Ryan Kastner, Ted Huffmire: Threats and Challenges in Reconfigurable Hardware Security. 334-345
• 
  Gavin Smith, Grant B. Wigley: High Level Languages for Reconfigurable Computing: An Equivalent to Third Generation Software Languages? 346-352

last updated on Sat May 18 04:52:03 2013 by the dblp team
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