ERSA 2004:
Las Vegas,
Nevada,
USA
Toomas P. Plaks (Ed.):
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, June 21-24, 2004, Las Vegas, Nevada, USA.
CSREA Press 2004, ISBN 1-932415-42-4 
@proceedings{DBLP:conf/ersa/2004,
editor = {Toomas P. Plaks},
title = {Proceedings of the International Conference on Engineering of
Reconfigurable Systems and Algorithms, ERSA'04, June 21-24, 2004,
Las Vegas, Nevada, USA},
booktitle = {ERSA},
publisher = {CSREA Press},
year = {2004},
isbn = {1-932415-42-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
MultiConference Keynote Paper
ERSA Keynote & Invited Talks
Reconfigurable Systems for Energy-Efficient Mobile Systems
Operating System Approaches for Reconfigurable Hardware
- Christian Plessl, Marco Platzner:
Virtualization of Hardware - Introduction and Survey.
63-69
- Heiko Kalte, Markus Koester, Boris Kettelhoit, Mario Porrmann, Ulrich Rückert:
A Comparative Study on System Approaches for Partially Reconfigurable Architectures.
70-76
- Manish Handa, Ranga Vemuri:
Area Fragmentation in Reconfigurable Operating Systems.
77-83
- Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignolet, Geert Deconinck, Rudy Lauwereins:
QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms.
84-92
Reconfigurable Supercomputing
- Timo Rolf Bretschneider, B. Ramesh, V. Gupta, Ian Vince McLoughlin:
Low-Cost Space-Borne Processing on a Reconfigurable Parallel Architecture.
93-99
- Duncan A. Buell, James P. Davis, Gang Quan, Sreesa Akella, Siddhaveerasharan Devarkal, P. Kancharla, Allen Michalski, Heather A. Wake:
Experiences with a Reconfigurable Computer.
100-108
HW/SW Environments for Reconfigurable Hardware
- Fred Ma, John P. Knight, Calvin Plett:
Physical Resource Binding for a Coarse Grain Reconfigurable Array.
109-115
- Razali Jidin, David L. Andrews, Douglas Niehaus:
Implementing Multi Threaded System Support for Hybrid FPGA/CPU Computational Components.
116-122
- Madhura Purnaprajna, Marek Reformat, Witold Pedrycz:
Genetic Algorithms in Hardware-Software Partitioning.
123-129
- Spencer Isaacson, Doran Wilde:
The Task-Resource Matrix: Control for a Distributed Reconfigurable Multi-Processor Hardware RTOS.
130-136
- Per Andersson, Krzysztof Kuchcinski:
Distinguished Paper: Automatic Local Memory Architecture Generation for Data Reuse in Custom Data Paths.
137-144
- Laurie A. Smith King, Miriam Leeser, Heather Quinn:
Dynamo: A Runtime Partitioning System.
145-154
Reconfigurable System-On a Chip (SOC) Architectures
Applications and Tools
- X. Zhang, Gabriel Dragffy, Anthony G. Pipe, Quan M. Zhu:
Partial-DNA Supported Artificial-Life in an Embryonic Array.
203-208
- Xin-Ming Huang, Jing Ma:
An FPGA-Based Accelerator for Multiphysics Modeling.
209-212
- Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri:
A Portable Face Recognition System Using Reconfigurable Hardware.
213-217
- Wenrui Gong, Gang Wang, Ryan Kastner:
A High Performance Application Representation for Reconfigurable Systems.
218-224
- Arvind Sudarsanam, Aravind Dasu, Sethuraman Panchanathan:
Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures.
225-231
- Zafer Gürdal, Tom Hartka, Mark Jones, Sun Wook Kim:
A Reconfigurable Approach to Structural Engineering Design Computations.
232-239
- Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh:
Incremental Timing Budget Management in Programmable Systems.
240-246
- Peter Bellows:
Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms.
247-258
Late Papers
- Chris Dick, Fred Harris:
On the Use of FPGAs for OFDM Signal Processing.
259-263
- Viktor K. Prasanna:
Invited Paper: Energy-Efficient Computations on FPGAs.
264-275
- Gokul Govindu, Viktor K. Prasanna, Vikash Daga, Sridhar Gangadharpalli, V. Sridhar:
Efficient Floating-point Based Block LU Decomposition on FPGAs.
276-279
- Jingzhao Ou, Viktor K. Prasanna:
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs.
280-283
- Ronald Scrofano, Viktor K. Prasanna:
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware.
284-292
- J. Yardley, K. Gilson:
A Reconfigurable Computing Model for Biological Research.
293-295
- Ali Akoglu, Aravind Dasu, Sethuraman Panchanathan:
Cluster Extraction for Hybrid FPGA Architecture in Computation Intensive Applications.
296
- Jesse Hunter, Peter Athanas, Cameron Patterson:
VTSim: A Virtex-II Device Simulator.
297-298
- Minoru Watanabe, Fuminori Kobayashi:
Testing Method for Optical Connections Using Gate Array Structure in ORGAs.
299-302
Posters
- Otsebele E. Nare, Lisa P. Mickens, Charles T. Johnson-Bey:
A Multi-Objective System Level Synthesis Approach to Reconfigurable Analog Technology.
303-304
- Xinzhong Guo, Jack S. N. Jean:
Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers.
305-306
- Herbert Walder, Samuel Nobs, Marco Platzner:
XF-Board: A Prototyping Platform for Reconfigurable Hardware Operating Systems.
306
- Aju M. Jacob, Ian A. Troxel, Alan D. George:
Distributed Configuration Management for Reconfigurable Cluster Computing.
307
- Vasanth Asokan, S. Mohan, Raj K. Nagarajan:
Hardware Software Codesign of the Xilinx Microkernel.
308
- Shinichi Koyama, Tomonori Izumi, Yukihiro Nakamura:
An Adaptive Load Distribution Model and Design on Self-Reconfigurable Logic Device.
309
- Pius Ng, David Zhao:
FFT Mapping on MathStar's FPOATM FilterBuilderTM Platform.
310
- Minoru Watanabe, Fuminori Kobayashi:
Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors.
311
- Austin Hung, William D. Bishop, Andrew A. Kennings:
Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips.
312
- Lodewijk T. Smit, Gerard J. M. Smit, Johann Hurink:
Run-Time Adaptation of a Reconfigurable Mobile UMTS Receiver.
313
- David Grant, William D. Bishop, Wayne M. Loucks:
A Flexible Processor for Research Prototyping.
314
- Mayur Srinivasan, Sethuraman Panchanathan:
Target Arhcitecture Automation for Reconfigurable Logic Blocks.
315
- Ling Zhuo, Viktor K. Prasanna:
Energy Performance of Floating-Point Matrix Multiplication on FPGAs.
316
- M. David Yeager, Wei Wang:
HARC: A Homogeneous Architecture reconfigurable Computer.
317
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