DSD 2011:
Oulu,
Finland
14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland.
IEEE 2011, ISBN 978-1-4577-1048-3
- Harmke de Groot:
Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care (Abstract).
3
- Harmke de Groot, Maryam Ashouei, Julien Penders, Valer Pop, Maja Vidojkovic, Bert Gyselinckx, Refet Firat Yazicioglu:
Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care.
4-10
- Kris Gaj:
Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware (Abstract).
11
- Menno Lindwer:
The Future of Data-Parallel Embedded Systems (Abstract).
12
- Ilya Levin, Osnat Keren:
Generalized If-Then-Else Operator for Compact Polynomial Representation of Multi Output Functions.
15-20
- Václav Dvorák, Petr Mikusek:
On the Cascade Implementation of Multiple-Output Sparse Logic Functions.
21-28
- Mohammad Hossein Neishaburi, Zeljko Zilic:
On Failure Rate Assessment Using an Executable Model of the System.
29-36
- Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer:
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip.
39-46
- Abdul Naeem, Axel Jantsch, Xiaowen Chen, Zhonghai Lu:
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.
47-54
- Mansour Shafaei, Ahmad Patooghy, Seyed Ghassem Miremadi:
Numeral-Based Crosstalk Avoidance Coding to Reliable NoC Design.
55-62
- Haoyuan Ying, Ashok Jaiswal, Thomas Hollstein, Klaus Hofmann:
A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication.
63-70
- Fahimeh Jafari, Shuo Li, Ahmed Hemani:
Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture.
73-80
- Behzad Salami, Morteza Saheb Zamani, Ali Jahanian:
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs.
81-87
- Muhammad Aqeel Wahlah, Kees Goossens:
PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC.
88-96
- Karthik Chandrasekar, Benny Akesson, Kees Goossens:
Improved Power Modeling of DDR SDRAMs.
99-108
- Alice M. Tokarnia, Pedro C. F. Pepe, Leandro D. Pagotto:
Path-Based Dynamic Voltage and Frequency Scaling Algorithms for Multiprocessor Embedded Applications with Soft Delay Deadlines.
109-116
- Andrew Nelson, Orlando Moreira, Anca Mariana Molnos, Sander Stuijk, Ba Thang Nguyen, Kees Goossens:
Power Minimisation for Real-Time Dataflow Applications.
117-124
- Sergey Ostroumov, Leonidas Tsiopoulos:
VHDL Code Generation from Formal Event-B Models.
127-134
- Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez:
Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage.
135-139
- Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França:
Hardware Reuse in Modern Application-Specific Processors and Accelerators.
140-147
- A. N. Nagamani, S. Nishchai:
Quaternary High Performance Arithmetic Logic Unit Design.
148-153
- Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers.
157-164
- Jesus Camacho, José Flich, José Duato, Hans Eberle, Wladek Olesinski:
Towards an Efficient NoC Topology through Multiple Injection Ports.
165-172
- Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture.
173-180
- Charly Bechara, Nicolas Ventroux, Daniel Etiemble:
Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems.
181-187
- Roland Dobai, Marcel Balaz:
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults.
191-196
- Nima Aghaee, Zebo Peng, Petru Eles:
Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation.
197-204
- Richard Ruzicka, Vaclav Simek:
Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles.
205-212
- Alireza Rohani, Hans G. Kerkhoff:
A Technique for Accelerating Injection of Transient Faults in Complex SoCs.
213-220
- Martin Straka, Jan Kastil, Zdenek Kotásek:
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems.
223-230
- Farid Lahrach, Abderrahim Doumar, Eric Châtelet:
Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems.
231-238
- Jia Huang, Jan Olaf Blech, Andreas Raabe, Christian Buckl, Alois Knoll:
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems.
239-246
- Yu Bai, Weidong Kuang:
Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance.
247-253
- Sebastian Isaza, Ernst Houtgast, Georgi Gaydadjiev:
HMMER Performance Model for Multicore Architectures.
257-261
- Antti Kamppi, Lauri Matilainen, Joni-Matti Määttä, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen:
Kactus2: Environment for Embedded Product Development Using IP-XACT and MCAPI.
262-265
- Paolo Maistri, Régis Leveugle:
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard.
266-269
- Georgios Keramidas, Nikolaos Strikos, Stefanos Kaxiras:
Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors.
270-273
- Philip Hodgers, Keanhong Boey, Máire O'Neill:
Power Spectral Density Side Channel Attack Overlapping Window Method.
274-278
- Caglar Kalaycioglu, Ilker Hamzaoglu:
Dynamic Power Estimation for Motion Estimation Hardware.
279-282
- Alfio Lombardo, Carla Panarello, Diego Reforgiato Recupero, Enrico Santagati, Giovanni Schembra:
A Module for Packet Hijacking in NetFPGA Platform.
283-286
- Jaroslav Borecky, Martin Kohlik, Pavel Kubalík, Hana Kubatova:
Fault Models Usability Study for On-line Tested FPGA.
287-290
- Thomas Plos, Martin Feldhofer:
Hardware Implementation of a Flexible Tag Platform for Passive RFID Devices.
293-300
- Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens:
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder.
301-308
- Tevfik Zafer Ozcan, Cagla Cakir, Mert Cetin, Ilker Hamzaoglu:
An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion.
309-315
- Martti Forsell, Ville Leppänen, Martti Penttonen:
Cost of Sparse Mesh Layouts Supporting Throughput Computing.
316-323
- Pierre-Henri Horrein, Christine Hennebert, Frédéric Pétrot:
An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms.
327-334
- Rohit Datta, Gerhard Fettweis, Zsolt Kollar, Péter Horváth:
FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY Design.
335-339
- Muhammad Awais, Ashwani Singh, Emmanuel Boutillon, Guido Masera:
A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder.
340-347
- Muhammad Aqeel Wahlah, Kees Goossens:
A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on Chip.
351-359
- Jiri Balcarek, Petr Fiser, Jan Schmidt:
Techniques for SAT-Based Constrained Test Pattern Generation.
360-366
- Michal Rumplík, Josef Strnadel:
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits.
367-374
- Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
An Enhanced Path Delay Fault Simulator for Combinational Circuits.
375-381
- Farshad Firouzi, Amir Yazdanbakhsh, Hamed Dorosti, Sied Mehdi Fakhraie:
Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling.
385-392
- Leandro Fiorin, Laura Micconi, Mariagiovanna Sami:
Design of Fault Tolerant Network Interfaces for NoCs.
393-400
- Fataneh Jafari, Mahdi Mosaffa, Siamak Mohammadi:
Designing Robust Asynchronous Circuits Based on FinFET Technology.
401-408
- Vahid Khorasani, Bijan Vosoughi Vahdat, Mohammad Mortazavi:
Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH Code.
409-413
- George Provelengios, Nikolaos S. Voros, Paris Kitsos:
Low Power FPGA Implementations of JH and Fugue Hash Functions.
417-421
- Ali Abbasinasab, Mehdi Mohammadi, Siamak Mohammadi, Svetlana N. Yanushkevich, Michael Smith:
Mutant Fault Injection in Functional Properties of a Model to Improve Coverage Metrics.
422-425
- Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Unified Architecture for BCD and Binary Adder/Subtractor.
426-429
- Michael D. Wilder, Robert Rinker:
Synthesizing Concurrent Synchronous Computing Machines from Interrupt-Driven Binaries.
430-433
- Ahmet Aris, Siddika Berna Örs, Gökay Saldamli:
Architectures for Fast Modular Multiplication.
434-437
- Takieddine Majdoub, Sébastien LeNours, Olivier Pasquier, Fabienne Nouvel:
Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication Protocol.
438-441
- Cor Meenderinck, Ben H. H. Juurlink:
Nexus: Hardware Support for Task-Based Programming.
442-445
- Mojtaba Valinataj:
Evaluation of Fault-Tolerant Routing Methods for NoC Architectures.
446-449
- Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos:
On the Design of Modulo 2^n+1 Multipliers.
453-459
- Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa:
Binary-to-RNS Conversion Units for moduli {2^n ± 3}.
460-467
- Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion.
468-475
- Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated Design Debugging in a Testbench-Based Verification Environment.
479-486
- Weiyun Lu, Martin Radetzki:
Efficient Fault Simulation of SystemC Designs.
487-494
- Marco Gerards, Christiaan Baaij, Jan Kuper, Matthijs Kooijman:
Higher-Order Abstraction in Hardware Descriptions with C?aSH.
495-502
- Hadrien A. Clarke, Kazuaki Murakami:
Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits.
503-508
- Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak:
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations.
511-518
- Romain Prolonge, Fabien Clermidy, Leonel Tedesco, Fernando Moraes:
Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots.
519-524
- Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout:
Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors.
525-532
- Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont:
Pre-silicon Characterization of NIST SHA-3 Final Round Candidates.
535-542
- Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms.
543-549
- Johannes Grinschgl, Armin Krieg, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
Modular Fault Injector for Multiple Fault Dependability and Security Evaluations.
550-557
- Petr Stembera, Martin Novotný:
Breaking Hitag2 with Reconfigurable Hardware.
558-563
- Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal:
Iteration-Based Trade-Off Analysis of Resource-Aware SDF.
567-574
- Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze:
SoC and Board Modeling for Processor-Centric Board Testing.
575-582
- Morteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal:
Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling.
583-590
- Apostolos P. Fournaris, Odysseas G. Koufopavlou:
Efficient CRT RSA with SCA Countermeasures.
593-599
- Daniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann:
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level.
600-607
- Tao Xie, Wolfgang Müller, Florian Letombe:
HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.
608-615
- Pablo Ituero, Marisa López-Vallejo, M. A. S. Marcos, Carlos Gómez Osuna:
On-chip Monitoring: A Light-Weight Interconnection Network Approach.
619-625
- Khalid Latif, Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Tiberiu Seceleanu, Pasi Liljeberg, Hannu Tenhunen:
Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures.
626-633
- Maryam Kamali, Luigia Petre, Kaisa Sere, Masoud Daneshtalab:
Formal Modeling of Multicast Communication in 3D NoCs.
634-642
- Kameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif, Pasi Liljeberg, Juha Plosila:
Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's.
643-648
- Xin Xin, Jens-Peter Kaps, Kris Gaj:
A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs.
651-657
- Tobias Vejda, Johann Großschädl, Dan Page:
A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary Fields.
658-666
- Junfeng Chu, Mohammed Benaissa:
A Novel Architecture of Implementing Error Detecting AES Using PRNS.
667-673
- Annelie Heuser, Michael Kasper, Werner Schindler, Marc Stöttinger:
How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power Analysis.
674-681
- Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz:
Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits.
685-692
- Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor:
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating.
693-700
- Satoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi:
A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations.
701-707
- Martijn Koedam, Sander Stuijk, Henk Corporaal:
Exploiting Inter and Intra Application Dynamism to Save Energy.
708-715
- Tolga Ovatman, Feza Buzluca:
Model Driven Cache-Aware Scheduling of Object Oriented Software for Chip Multiprocessors.
719-726
- Simon Yuan, Li Hsien Yoong, Partha S. Roop:
Compiling Esterel for Multi-core Execution.
727-735
- Lina Sawalha, Sonya Wolff, Monte P. Tull, Ronald D. Barnes:
Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors.
736-745
- Alessandro Bardine, Pierfrancesco Foglia, Francesco Panicucci, Marco Solinas, Julio Sahuquillo:
Energy Behaviour of NUCA Caches in CMPs.
746-753
- Giovanni Danese, Francesco Leporati, Alessandra Majani, Giulia Matrone, Enrico Merlino:
A Wearable Intelligent System for the Health of Expectant Mom's and of Their Children.
757-763
- Choong Geun Lee, Vasily G. Moshnyaga, Koji Hashimoto:
Embedded System for Camera-Based TV Power Reduction.
764-768
- Guido Matrella, Davide Marani:
An Embedded Video Sensor for a Smart Traffic Light.
769-776
- Alessandro Barenghi, Guido Bertoni, Fabrizio De Santis, Filippo Melzani:
On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks.
777-785
- Mohammad Maghsoudloo, Hamid R. Zarandi, Saadat Pour-Mozafari, Navid Khoshavi:
Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring.
789-792
- Nicola Bombieri, Franco Fummi, Sara Vinco, Davide Quaglia:
Automatic Interface Generation for Component Reuse in HW-SW Partitioning.
793-796
- Tom Van Leeuwen, Rene van Leuken:
A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital Circuits.
797-800
- Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers.
801-804
- Luka B. Daoud, M. El-Sayed Ragab, Victor Goulart:
Faster Processor Allocation Algorithms for Mesh-Connected CMPs.
805-808
- Ghazaleh Nazarian, Christos Strydis, Georgi Gaydadjiev:
Compatibility Study of Compile-Time Optimizations for Power and Reliability.
809-813
- Paris Kitsos, Nicolas Sklavos, Athanassios N. Skodras:
An FPGA Implementation of the ZUC Stream Cipher.
814-817
- Ashkan Beyranvand Nejad, Anca Mariana Molnos, Kees G. W. Goossens:
A Unified Execution Model for Data-Driven Applications on a Composable MPSoC.
818-822
Last update Thu May 24 04:16:31 2012
CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page