Keynote Speakers

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  Jan M. Rabaey: Design Without Borders. 3
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  Chi-Foon Chan: Semiconductor and EDA Challenges: Still Lots To Solve! 4
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  Jan M. Rabaey, Yuen-Hui Chee, David Chen, Luca De Nardis, Simone Gambini, Davide Guermandi, Michael Mark, Nathan Pletcher: Short Distance Wireless, Dense Networks, and Their Opportunities. 7
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  Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Mohammad A. Makhzan, Stanley Cheng: Error-Aware Design. 8-15
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  Mladen Berekovic: Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring. 16-18

Regular Papers

• 
  Mohammad Mirza-Aghatabar, Somayyeh Koohi, Shaahin Hessabi, Massoud Pedram: An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models. 19-26
• 
  Jan Willem van den Brand, Marco Bekooij: Streaming consistency: a model for efficient MPSoC design. 27-34
• 
  Christian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, R. Peters: A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture. 35-42
• 
  Mohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi: Design and Implementation of a 50MHZ DXT CoProcessor. 43-50
• 
  Gerald Hempel, Christian Hochberger: A resource optimized Processor Core for FPGA based SoCs. 51-58
• 
  Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek: Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. 59-62
• 
  Arno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen: Decoupling of Computation and Communication with a Communication Assist. 63-68
• 
  Tsutomu Sasao, Munehiro Matsuura: An Implementation of an Address Generator Using Hash Memories. 69-76
• 
  Volker Hampel, Peter Sobe, Erik Maehle: Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor. 77-84
• 
  Panagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold: Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction. 85-93
• 
  Martin Novotný, Jan Schmidt: General Digit-Serial Normal Basis Multiplier with Distributed Overlap. 94-101
• 
  Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello: An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. 102-108
• 
  Santosh Ghosh, Monjur Alam, Indranil Sengupta, Dipanwita Roy Chowdhury: A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography. 109-115
• 
  Nadia Nedjah, Luiza de Macedo Mourelle: A Hardware/Software Co-design vs. Hardware Implementation of the Modular Exponentiation Using the Sliding-Window Method with Constant-Length Partitioning. 116-123
• 
  Falk Salewski, Adam Taylor: Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative Survey. 124-131
• 
  Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo: Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. 132-137
• 
  Scott Miller, Mihai Sima, Michael McGuire: Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays. 138-146
• 
  Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt: A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator. 147-150
• 
  Mark G. Arnold, Panagiotis D. Vouzis: A Serial Logarithmic Number System ALU. 151-156
• 
  Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi: Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. 157-164
• 
  Joseph C. Libby, Kenneth B. Kent: An Embedded Implementation of the Microsoft Common Language Infrastructure. 165-172
• 
  Kalle Holma, Mikko Setälä, Erno Salminen, Timo D. Hämäläinen: Evaluating the Model Accuracy in Automated Design Space Exploration. 173-180
• 
  Ismail Assayad, Sergio Yovine: P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications. 181-188
• 
  Amir Hossein Ghamarian, Sander Stuijk, Twan Basten, Marc Geilen, Bart D. Theelen: Latency Minimization for Synchronous Data Flow Graphs. 189-196
• 
  Eugene Goldberg, Kanupriya Gulati: On Complexity of Internal and External Equivalence Checking. 197-206
• 
  Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: The Criteria of Functional Delay Test Quality Assessment. 207-214
• 
  Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch: RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. 215-221
• 
  Youssef Serrestou, Vincent Beroulle, Chantal Robach: Functional Verification of RTL Designs driven by Mutation Testing metrics. 222-227
• 
  Peter Poplavko, Twan Basten, Jef L. van Meerbergen: Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism. 228-235
• 
  Carlo Brandolese, D. Crespi, Laura Frigerio, Fabio Salice: A New Framework for Design and Simulation of Complex Hardware/Software Systems. 236-243
• 
  Chiyuan Ma, Shuming Chen: A DRAM Precharge Policy Based on Address Analysis. 244-248
• 
  Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis: High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. 249-256
• 
  Katsumi Wasaki, Toshiaki Harai, Tamotsu Hayashi, Ken-ichi Arai: Controller Design and Verification for A Pipeline Image Processor based on An Extended Petri net. 257-260
• 
  Andreas Lankes, Thomas Wild, Johannes Zeppenfeld: Power Estimation of Time Variant SoCs with TAPES. 261-264
• 
  Ping Hang Cheung, Kecheng Hao, Fei Xie: Component-Based Hardware/Software Co-Simulation. 265-270
• 
  Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri: Toggle Equivalence Preserving (TEP) Logic Optimization. 271-279
• 
  Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. 280-287
• 
  Ana Fuentes Martinez, Krzysztof Kuchcinski: Graph Matching Constraints for Synthesis with Complex Components. 288-295
• 
  Jesús Barba, Fernando Rincón, Francisco Moya, Felix Jesús Villanueva, David Villa, Julio Dondo, Juan Carlos López: OOCE: Object-Oriented Communication Engine for SoC Design. 296-302
• 
  Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera: Timing- / Power-Optimization for Digital Logic Based on Standard Cells. 303-306
• 
  Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan: Energy Based Design Space Exploration of Multiprocessor VLIW Architectures. 307-310
• 
  Moonvin Song, Sang Hoon Hong, Yunmo Chung: Reducing the Overhead of Real-Time Operating System through Reconfigurable Hardware. 311-316
• 
  Kolin Paul, Joel Porquet, Josep Llosa: Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. 317-324
• 
  J. V. R. Ravindra, M. B. Srinivas: A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. 325-330
• 
  Hosna Jabbari, Jon C. Muzio, Lin Sun: A New Class of Cellular Automata. 331-338
• 
  Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. 339-346
• 
  Sharon Van Schaick, Kenneth B. Kent: Analysis of Variable Reordering on the QMDD Representation of Quantum Circuits. 347-352
• 
  Manoj Gupta, Fermín Sánchez, Josep Llosa: Merge Logic for Clustered Multithreaded VLIW Processors. 353-360
• 
  Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni: Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems. 361-368
• 
  Giuseppe Gentile, Massimo Rovini, Luca Fanucci: Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes. 369-375
• 
  Daniele Audino, Federico Baronti, Andrea Lazzeri, Roberto Roncella, Roberto Saletti: FPGA/DSP-based Configurable Multi-Channel Counter. 376-382
• 
  Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo: Design and Implementation of a 90nm Low bit-rate Image Compression Core. 383-389
• 
  Alei Liang, Kejia Liu, Xiaoyong Li, Haibing Guan: FATTY: A Reliable FAT File System. 390-395
• 
  Sebastian Kinder, Rolf Drechsler: Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. 396-403
• 
  Matti Eteläperä, Janne Vatjus Anttila, Juha Pekka Soinimen: Architecture Exploration of 3D Video Recorder Using Virtual Platform Models. 404-411
• 
  Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo: FPGA-based Road Traffic Videodetector. 412-419
• 
  Miroslav Svéda, Roman Trchalik: Safety and Security-driven Design of Networked Embedded Systems. 420-423
• 
  Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin: MPSoC memory optimization for digital camera applications. 424-427
• 
  Dante Del Corso, Claudio Passerone, Leonardo Maria Reyneri, Claudio Sansoè, Marco Borri, Stefano Speretta, Maurizio Tranchero: Architecture of a Small Low-Cost Satellite. 428-431
• 
  Jinbo Xu, Yong Dou, Junfeng Li, Xingming Zhou, Qiang Dou: FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications. 432-435
• 
  Silvia Franchini, Antonio Gentile, M. Grimaudo, C. A. Hung, Sandro Impastato, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile: A Sliced Coprocessor for Native Clifford Algebra Operations. 436-439
• 
  Federico Baronti, Francesco Lenzi, Roberto Roncella, Roberto Saletti: A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems. 440-443
• 
  Serkan Oktem, Ilker Hamzaoglu: An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. 444-447
• 
  Esra Sahin, Ilker Hamzaoglu: An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. 448-454
• 
  Agustin Barberis, Leonardo Barboni, Maurizio Valle: Evaluating Energy Consumption in Wireless Sensor Networks Applications. 455-462
• 
  Alex Janek, Christoph Trummer, Christian Steger, Reinhold Weiss, Josef Preishuber-Pfluegl, Markus Pistauer: Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting Devices. 463-462
• 
  Abdalkarim Awad, Thorsten Frunzke, Falko Dressler: Adaptive Distance Estimation and Localization in WSN using RSSI Measures. 471-478
• 
  Seungjae Lee, Changhwa Kim, Sangkyung Kim: A Proposal of New Join Operators for Sensor Network Databases. 479-484
• 
  Matthew D'Souza, Konstanty Bialkowski, Adam Postula, Montserrat Ros: A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction Applications. 485-494
• 
  Christoph Puttmann, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert: GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. 495-502
• 
  Erno Salminen, Ari Kulmala, Timo D. Hämäläinen: On network-on-chip comparison. 503-510
• 
  Mikael Millberg, Axel Jantsch: Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy. 511-518
• 
  D. Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra: Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer. 519-526
• 
  Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel: Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures. 527-534
• 
  Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: On-Chip Verification of NoCs Using Assertion Processors. 535-538
• 
  Leandro Fiorin, Cristina Silvano, Mariagiovanna Sami: Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations. 539-542
• 
  Luciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli: NoC Topologies Exploration based on Mapping and Simulation Models. 543-546
• 
  Gianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola: Application-Specific Topology Design Customization for STNoC. 547-550
• 
  Pekka Rantala, Jouni Isoaho, Hannu Tenhunen: Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip. 551-555
• 
  Paolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo: On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs. 556-562
• 
  Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the Construction of Small Fully Testable Circuits with Low Depth. 563-569
• 
  David Roberts, Nam Sung Kim, Trevor N. Mudge: On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology. 570-578
• 
  Andrzej Krasniewski: Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. 579-586
• 
  Silvio Misera, Heinrich Theodor Vierhaus, André Sieber: Fault Injection Techniques and their Accelerated Simulation in SystemC. 587-595
• 
  Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar: Hybrid BIST Optimization Using Reseeding and Test Set Compaction. 596-603
• 
  Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen: Fault Diagnosis in Integrated Circuits with BIST. 604-610
• 
  Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. 611-618
• 
  Elham K. Moghaddam, Shaahin Hessabi: An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. 619-625
• 
  Richard Ruzicka, Josef Strnadel: Test Controller Synthesis Constrained by Circuit Testability Analysis. 626-633
• 
  Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai: Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. 634-640
• 
  Christian J. Hescott, Drew C. Ness, David J. Lilja: Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment. 641-648
• 
  M. Marshall, G. Russell: A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor. 649-656
• 
  Petr Fiser: Pseudo-Random Pattern Generator Design for Column-Matching BIST. 657-663
• 
  Haridimos T. Vergos: An Efficient BIST Scheme for Non-Restoring Array Dividers. 664-667
• 
  Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus: Hierarchical Identification of Untestable Faults in Sequential Circuits. 668-671
• 
  Federico Baronti, Roberto Roncella, Roberto Saletti, Paolo D'Abramo, L. Di Piro, H. Fabian, M. Giardi: The importance of At-Speed Scan Testing: an industrial experience. 672-675
• 
  Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka: Online Protocol Testing for FPGA Based Fault Tolerant Systems. 676-679
• 
  Johann Großschädl, Stefan Tillich, Alexander Szekely: Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor. 680-689

last updated on Tue May 21 01:57:16 2013 by the dblp team
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