DSD 2006:
Dubrovnik,
Croatia
Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia.
IEEE Computer Society 2006, ISBN 0-7695-2609-8 
Keynote Papers
Systems-on-a-Chip/In-a-package
- Klaus Waldschmidt:
Robustness in SOC Design.
27-36
- Zhonghai Lu, Ingo Sander, Axel Jantsch:
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.
37-44
- Sander Stuijk, Twan Basten, Marc Geilen, Amir Hossein Ghamarian, Bart D. Theelen:
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication.
45-52
- Frédéric Pétrot, Alain Greiner, Pascal Gomez:
On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures.
53-60
- Sara Román Navarro, Hortensia Mecha, Daniel Mozos, Julio Septién:
Partition Based Dynamic 2D HW Multitasking Management.
61-70
- Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha:
Global Analysis of Resource Arbitration for MPSoC.
71-78
- Alokika Dash, Peter Petrov:
Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering.
79-82
- Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen:
Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA.
83-88
- Hanene Ben Fradj, Cécile Belleudy, Michel Auguin:
Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization.
89-96
- Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten:
A Monitoring-Aware Network-on-Chip Design Flow.
97-106
- Reid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner:
A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing.
107-115
- Michael Freeman, Thimal Jayasooriya:
A Hardware IP-Core for Information Retrieval.
115-122
- Kyriakos Stavrou, Pedro Trancoso:
Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems.
123-126
- Michael Freeman:
Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors.
127-130
- Martin Delvai, Andreas Steininger:
Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods.
131-138
Programmable/Re-configurable Architectures
- Pavel Kubalík, Radek Dobias, Hana Kubatova:
Dependable Design for FPGA Based on Duplex System and Reconfiguration.
139-145
- Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni:
A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks.
146-154
- Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas:
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n).
155-159
- Svetislav Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa:
Application Specific Instruction Set Processor for Adaptive Video Motion Estimation.
160-167
- Haridimos T. Vergos, Costas Efstathiou:
Novel Modulo 2n + 1 Multipliers.
168-175
- Eryk Laskowski, Marek Tudruj:
Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources.
176-179
- George Kornaros:
BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory.
180-188
- Fritz Mayer-Lindenberg:
Design and Application of a Scalable Embedded Systems' Architecture with an FPGA Based Operating Infrastucture.
189-196
- Sylvain Collange, Jérémie Detrey, Florent de Dinechin:
Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis.
197-203
- Jamel Tayeb, Smaïl Niar:
Adapting EPIC Architecture's Register Stack for Virtual Stack Machines.
204-210
- Ahmet Akkas:
Dual-Mode Quadruple Precision Floating-Point Adder.
211-220
- Pedro Trancoso:
Adaptive High-End Microprocessor for Power-Performance Efficiency.
221-228
- Filipa Duarte, Stephan Wong:
Profiling Bluetooth and Linux on the Xilinx Virtex II Pro.
229-235
- Viay Holimath, Javier D. Bruguera:
A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table.
236-239
- Sylvain Huet, Emmanuel Casseau, Olivier Pasquier:
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms.
240-250
- Martin Stáva, Ondrej Novák:
Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW.
251-256
- Petros Oikonomakos, Simon W. Moore:
An Asynchronous PLA with Improved Security Characteristics.
257-264
- Giovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo:
Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information.
265-268
- Roberto R. Osorio, Javier D. Bruguera:
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems.
269-274
System,
Hardware and Embedded Software Specification,
Modeling and Validation
- Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber:
A Mixed Language Fault Simulation of VHDL and SystemC.
275-279
- Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser:
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar.
280-287
- Ines Viskic, Rainer Dömer:
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models.
288-294
- Adam Smyk, Marek Tudruj:
Prototyping Parallel FDTD Programs by Macro Data Flow Graph Analysis.
295-304
- Armando Sánchez-Peña, Pedro P. Carballo, Luz García, Antonio Núñez:
VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems.
305-312
- Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng:
Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*.
313-322
- Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Transition Fault Test Reuse.
323-330
- Muhammad Waseem, Ludovic Apvrille, Rabéa Ameur-Boulifa, Sophie Coudert, Renaud Pacalet:
Abstract Application Modeling for System Design Space Exploration.
331-337
- Gianluca Casarosa, Michele Apuzzo, Luca Fanucci, Bruno Sarti:
Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites.
338-345
- Liam Noonan, Colin Flanagan:
Utilising Evolutionary Approaches and Object Oriented Techniques for Design Space Exploration.
346-352
- Jaan Raik, Raimund Ubar, Taavi Viilukas:
High-Level Decision Diagram based Fault Models for Targeting FSMs.
353-358
- Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov:
Cascade Scheme for Concurrent Errors Detection.
359-368
System,
Hardware and Embedded Software Synthesis
- Petr Fiser, Hana Kubatova:
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications.
369-376
- Anna Bernasconi, Valentina Ciriani:
DRedSOP: Synthesis of a New Class of Regular Functions.
377-384
- Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski:
Multi-objective Optimal FSM State Assignment.
385-396
- Lech Józwiak, Sien-An Ong:
Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs.
397-406
- Javier D. Bruguera, Roberto R. Osorio:
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization.
407-414
- Michael Cowell, Adam Postula:
Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs.
415-422
- José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López:
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.
423-432
- Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus:
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes.
433-438
- Jacques J. A. Fournier, Simon W. Moore:
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography.
439-446
- Arjan C. Dam, Michel G. J. Lammertink, Kenneth C. Rovers, Johan Slagman, Arno M. Wellink:
Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard.
447-455
- Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar:
A Power-Aware Technique for Functional Units in High-Performance Processors.
456-459
- Vít Fábera, Vlastimil Jánes, Mária Jánesová:
Automata Construct with Genetic Algorithm.
460-463
- Tero Vallius, Juha Röning:
ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems.
464-474
- Mark G. Arnold:
A RISC Processor with Redundant LNS Instructions.
475-482
- Markus Damm:
State Assignment for Detecting Erroneous Transitions in Finite State Machines.
483-490
- Qing K. Zhu:
Memory Generation and Power Distribution In SOC.
491-495
- Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski:
A Graph Based Algorithm for Data Path Optimization in Custom Processors.
496-503
- Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina:
Testability Estimation Based on Controllability and Observability Parameters.
504-514
Emerging Technologies,
System Paradigms and Design Methodologies
Apllications of (embedded) Digital Systems
- Massimo Rovini, Francesco Rossi, Pasquale Ciao, Nicola L'Insalat, Luca Fanucci:
Layered Decoding of Non-Layered LDPC Codes.
537-544
- Francesco Rossi, Massimo Rovini, Luca Fanucci:
Design and Validation of Digital Channels for a Galileo Receiver Prototype.
545-549
- Martin Novotný, Jan Schmidt:
Two Architectures of a General Digit-Serial Normal Basis Multiplier.
550-553
- Enric Pastor, Juan López, Pablo Royo:
An Embedded Architecture for Mission Control of Unmanned Aerial Vehicles.
554-560
- Andrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini:
Design of a Low-Power Digital Core for Passive UHF RFID Transponder.
561-568
- Gian Mario Bertolotti, Andrea Cristiani, R. Gandolfi, Remo Lombardi:
A Portable System for Measuring Human Body Movement.
569-576
- Panu Hämäläinen, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen:
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core.
577-583
- Yan Zhang, Jussi Roivainen, Aarne Mämmelä:
Clock-Gating in FPGAs: A Novel and Comparative Evaluation.
584-590
Spl. Session on Resource-Aware Sensor Network Systems
SessionWSN
Spl. Session on Low-Power and High-Performance Networks-on-Chip
- Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen:
A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.
641-648
- Guang Liang, Axel Jantsch:
Adaptive Power Management for the On-Chip Communication Network.
649-656
- Tobias Bjerregaard, Jens Sparsø:
Packetizing OCP Transactions in the MANGO Network-on-Chip.
657-664
- Christian Neeb, Norbert Wehn:
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip.
665-672
- Sandro Penolazzi, Axel Jantsch:
A High Level Power Model for the Nostrum NoC.
673-676
- Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng:
Off-Line Testing of Delay Faults in NoC Interconnects.
677-680
- Rikard Thid, Ingo Sander, Axel Jantsch:
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads.
681-688
- Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu:
Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm.
689-695
- Rickard Holsmark, Maurizio Palesi, Shashi Kumar:
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.
696-703
Last update Tue Feb 14 03:53:58 2012
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