DFT 2009:
Chicago,
Illinois,
USA
Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor (Eds.):
24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, 7-9 October 2009, Chicago, Illinois, USA.
IEEE Computer Society 2009 
Keynote Talk
Session 1 - BIST and on-chip test generation
Session 2 - Design for Fault Tolerance I
Invited Talk
Session 3 - Emerging technologies
- Nor Zaidi Haron, Said Hamdioui:
Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories.
85-93
- Aaron Dingler, M. Jafar Siddiq, Michael T. Niemier, Xiaobo Sharon Hu, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod:
Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power.
94-102
- Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi:
Coded DNA Self-Assembly for Error Detection/Location.
103-111
- Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi:
Errors in DNA Self-Assembly by Synthesized Tile Sets.
112-120
Keynote Talk
- Naveed A. Sherwani:
Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs.
123-123
Session 4 - Error detection
Session 5 - Yield analysis and dependability
- Jenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren:
Characterization of Gain Enhanced In-Field Defects in Digital Imagers.
155-163
- Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang:
Analysis of Resistive Open Defects in a Synchronizer.
164-172
- Cristiana Bolchini, Fabrizio Castro, Antonio Miele:
A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems.
173-181
- Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe:
On the Functional Qualification of a Platform Model.
182-190
Session 6 - Design for Fault Tolerance II
Invited Talk
Session 7 - Interactive Poster Session
- Takumi Hoshi, Kazuteru Namba, Hideo Ito:
Testing of Switch Blocks in Three-Dimensional FPGA.
227-235
- Jianwei Dai, Lei Wang:
A Study of Side-Channel Effects in Reliability-Enhancing Techniques.
236-244
- Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue:
Reliability and Performance Analysis of FPGA-Based Fault Tolerant System.
245-253
- Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis:
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.
254-262
- Snehal Udar, Dimitri Kagaris:
Minimizing Observation Points for Fault Location.
263-267
- Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi:
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms.
268-276
- Meng Zhang, Anita Lungu, Daniel J. Sorin:
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms.
277-285
- Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino:
System Level Testing via TLM 2.0 Debug Transport Interface.
286-294
- Nader Alawadhi, Ozgur Sinanoglu:
Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments.
295-303
- Syed Zafar Shazli, Mehdi Baradaran Tahoori:
Transient Error Detection and Recovery in Processor Pipelines.
304-312
- Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi:
Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels.
313-321
- Yehua Su, Wenjing Rao:
Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis.
322-330
- Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud:
Complementary Formal Approaches for Dependability Analysis.
331-339
- Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR).
340-348
- Yu Liu, Kaijie Wu:
An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level.
349-357
- Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.
358-366
- Yuu Maeda, Haruhiko Kaneko:
Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes.
367-375
Keynote Talk
Session 8 - Testing and Design for Test
- Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Improving the Detectability of Resistive Open Faults in Scan Cells.
383-391
- Luca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin:
An Incremental Approach to Functional Diagnosis.
392-400
- Stelios Neophytou, Maria K. Michael, Kyriakos Christou:
Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning.
401-409
- Unni Chandran, Dan Zhao:
Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip.
410-418
Invited Talk
- Yiorgos Makris:
Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors.
421-421
- Adit D. Singh:
A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS.
422-422
Session 9 - Error detection and correction
Invited Talk
- Li-C. Wang:
Data Learning Techniques for Functional/System Fmax Prediction.
451-451
Last update Thu May 24 04:16:21 2012
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