Cover

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  Title Page.
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  Copyright.

Introduction

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  Message from the Symposium Chairs.
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  Committees.

Yield Analysis and Modeling

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  Mehdi Baradaran Tahoori: Defects, Yield, and Design in Sublithographic Nano-electronics. 3-11
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  Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: An ILP Formulation for Yield-driven Architectural Synthesis. 12-20
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  Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Design and Analysis of Self-Repairable MEMS Accelerometer. 21-32

Scan Design and Test Data Compression

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  Jinkyu Lee, Nur A. Touba: Low Power BIST Based on Scan Partitioning. 33-41
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  Samuel I. Ward, Chris Schattauer, Nur A. Touba: Using Statistical Transformations to Improve Compression for Linear Decompressors. 42-50
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  Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic: Securing Scan Design Using Lock and Key Technique. 51-62

Reconfiguration

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  Masaru Fukushi, Yusuke Fukushima, Susumu Horiguchi: A Genetic Approach for the Reconfiguration of Degradable Processor Arrays. 63-71
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  Luca Breveglieri, Israel Koren, Paolo Maistri: Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard. 72-80
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  Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu: An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. 81-92

Error Correcting Codes and Circuits

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  Haruhiko Kaneko: Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment. 93-101
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  Siavash Bayat Sarmadi, M. Anwar Hasan: Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme. 102-110
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  Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano: A Self Checking Reed Solomon Encoder: Design and Analysis. 111-119
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  Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara: Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. 120-130

Fault Detection and Tolerance for Sensor and Flash Memory

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  B. Saillet, Jean Michel Portal, Didier Née: Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. 131-139
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  Cory Jung, Mohammad Hadi Izadi, Michelle L. La Haye: Noise Analysis of Fault Tolerant Active Pixel Sensors. 140-148
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  Glenn H. Chapman, Israel Koren, Zahava Koren, Jozsef Dudas, Cory Jung: On-Line Identification of Faults in Fault-Tolerant Imagers. 149-157
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  Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali: Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems. 158-168

Delay Fault Test and Timing Consideration

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  Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak: The Other Side of the Timing Equation: a Result of Clock Faults. 169-177
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  Lei Wu, D. M. H. Walker: A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. 178-186
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  Nisar Ahmed, Mohammad Tehranipoor: Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. 187-198

Defect and Fault Tolerant Design in QCA Circuits

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  Mariam Momenzadeh, Jing Huang, Fabrizio Lombardi: Defect Characterization and Tolerance of QCA Sequential Devices and Circuits. 199-207
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  Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi: Modeling QCA Defects at Molecular-level in Combinational Circuits. 208-216
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  Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer: QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. 217-228

Interconnect Test

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  David M. Horan, Richard A. Guinee: A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences. 229-237
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  Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh: Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. 238-246
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  Roberto Gómez, Alejandro Girón, Víctor H. Champac: Test of Interconnection Opens Considering Coupling Signals. 247-258

Case Studies and Applications

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  Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano: FPGA oriented design of parity sharing RS codecs. 259-265
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  Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi: A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems. 266-274
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  G. Cellere, Alessandro Paccagnella, A. Visconti, M. Bonanomi: Soft Errors induced by single heavy ions in Floating Gate memory arrays. 275-284
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  Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi: On the Modeling and Analysis of Jitter in ATE Using Matlab. 285-293
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  Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi: Data Dependent Jitter (DDJ) Characterization Methodology. 294-304

Interactive Session

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  Mohammad Tehranipoor: Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure. 305-313
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  Erik Schüler, Luigi Carro: Reliable Digital Circuits Design using Sigma-Delta Modulated Signals. 314-324
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  Dilip P. Vasudevan, Parag K. Lala: A Technique for Modular Design of Self-Checking Carry-Select Adder. 325-333
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  Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto: A model of soft error effects in generic IP processors. 334-342
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  Vladimir Ostrovsky, Ilya Levin: Implementation of Concurrent Checking Circuits by Independent Sub-circuits. 343-351
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  Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra: Multiple Transient Faults in Logic: An Issue for Next Generation ICs. 352-360
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  Fang Yu, Chung-Hung Tsai, Yao-Wen Huang, D. T. Lee, Hung-Yau Lin, Sy-Yen Kuo: Efficient Exact Spare Allocation via Boolean Satisfiability. 361-370
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  Jia Di, Parag K. Lala, Dilip P. Vasudevan: On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. 371-379
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  Bhushan Vaidya, Mehdi Baradaran Tahoori: Delay Test Generation with All Reachable Output Propagation and Multiple Excitations. 380-388
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  Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. 389-397
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  Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz: On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. 398-405
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  Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda: Should Illinois-Scan Based Architectures be Centralized or Distributed? 406-414
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  Leonard Lee, Sean H. Wu, Charles H.-P. Wen, Li-C. Wang: On Generating Tests to Cover Diverse Worst-Case Timing Corners. 415-426

Approaches for Soft Error

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  Wei Zhang: Computing Cache Vulnerability to Transient Errors and Its Implication. 427-435
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  Luca Sterpone, Massimo Violante: A design flow for protecting FPGA-based systems against single event upsets. 436-444
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  Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. 445-453
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  Jeetendra Kumar, Mehdi Baradaran Tahoori: A Low Power Soft Error Suppression Technique for Dynamic Logic. 454-462
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  Hossein Asadi, Mehdi Baradaran Tahoori: Soft Error Modeling and Protection for Sequential Elements. 463-474

On-line and Concurrent Fault Detection

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  Irith Pomeranz, Sudhakar M. Reddy: Recovery During Concurrent On-Line Testing of Identical Circuits. 475-483
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  Song Peng, Rajit Manohar: Efficient Failure Detection in Pipelined Asynchronous Circuits. 484-493
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  Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero: On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors. 494-504

Fault and Error Tolerant Systems

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  Masato Kitakami, Manabu Sueishi: Fault-Tolerant Wormhole Switching with Backtracking Capability. 505-513
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  Hyukjune Chung, Antonio Ortega: Analysis and Testing for Error Tolerant Motion Estimation. 514-522
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  In Suk Chong, Antonio Ortega: Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms. 523-534

Test Scheduling and Software-based Test

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  Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis: Software-Based Self-Test for Pipelined Processors: A Case Study. 535-543
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  Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty: Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. 544-551
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  Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar: Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems. 552-562

Testing and Design for Analog Circuits

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  Shaolei Quan, Meng-Yao Liu, Chin-Long Wey: Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress. 563-572
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  Yukiya Miura: Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test. 573-581
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  Michael Wieckowski, John Liobe, Quentin Diduck, Martin Margala: A New Test Methodology For DNL Error In Flash ADC's. 582-590
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  Sadeka Ali, Gregory Briggs, Martin Margala: A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. 591-600

last updated on Sat May 25 04:53:57 2013 by the dblp team
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