DFT 2004: Cannes, France

19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings. IEEE Computer Society 2004, ISBN 0-7695-2241-6
Contents

Yield and Defects I

Roman Barsky, Israel A. Wagner:
Reliability and Yield: A Joint Defect-Oriented Approach. 2-10
Xiaopeng Wang, Marco Ottavi, Fred J. Meyer, Fabrizio Lombardi:
On The Yield of Compiler-Based eSRAMs. 11-19
Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu:
Failure Factor Based Yield Enhancement for SRAM Designs. 20-28

Yield and Defects II

Jing Huang, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi:
Defect Characterization for Scaling of QCA Devices. 30-38
Alexandre Schmid, Yusuf Leblebici:
A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. 39-47
Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi:
Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. 48-56

Optoelectronics

Michelle L. La Haye, Glenn H. Chapman, Cory Jung, Desmond Y. H. Cheung, Sunjaya Djaja, Benjamin Wang, Gary Liaw, Yves Audet:
Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS). 58-66
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali:
Defect Avoidance in a 3-D Heterogeneous Sensor. 67-75

Defect and Fault Tolerance

Ammar Aljer, Philippe Devienne:
Co-Design and Refinement for Safety Critical Systems. 78-86
Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. 87-95
Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi:
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars. 96-104

Memory Test

Stefano Bertazzoni, Domenico Di Giovenale, Marcello Salmeri, Arianna Mencattini, Adelio Salsano, M. Florean, Jeffery Wyss, Ricardo Rando, Silvano Lora:
Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis. 106-110
Xiaopeng Wang, Marco Ottavi, Fabrizio Lombardi:
Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs. 111-119
Baosheng Wang, Yuejian Wu, André Ivanov:
Designs for Reducing Test Time of Distributed Small Embedded SRAMs. 120-128

Diagnosis

Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri:
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost. 130-138
Shi-Yu Huang:
A Fading Algorithm For Sequential Fault Diagnosis. 139-147

Error Correcting Codes

Hamidreza Hashempour, Fabrizio Lombardi:
Compression of VLSI Test Data by Arithmetic Coding. 150-157
Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Data Integrity Evaluations of Reed Solomon Codes for Storage Systems. 158-164
Ping-Hsun Hsieh, Ing-Yi Chen, Yu-Ting Lin, Sy-Yen Kuo:
An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems. 165-172

Interconnect Faults

Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel:
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. 174-182
Irith Pomeranz, Sudhakar M. Reddy:
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. 183-190
Michele Favalli:
"Victim Gate" Crosstalk Fault Model. 191-199

RF and High Speed Circuits

Martin Omaña, Daniele Rossi, Cecilia Metra:
Fast and Low-Cost Clock Deskew Buffer. 202-210
Tejasvi Das, Anand Gopalan, Clyde Washburn, P. R. Mukund:
Dynamic Input Match Correction in RF Low Noise Amplifiers. 211-219
Jerzy Dabrowski, Javier Gonzalez Bayon:
Mixed Loopback BiST for RF Digital Transceivers. 220-228

Analog Testing

Yukiya Miura:
Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method. 230-238
Adão Antônio de Souza Jr., Luigi Carro:
Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities. 239-247

Interactive Session

Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco:
Coupling Different Methodologies to Validate Obsolete Microprocessors. 250-255
Ireneusz Gosciniak:
A New Approach to Linear Connections Building BIST Structure Based on CSTP Structure. 256-263
Najwa Aaraj, Anis Nazer, Ali Chehab, Ayman I. Kayssi:
Transient Current Testing of Dynamic CMOS Circuits. 264-271
Brian Peng, Ing-Yi Chen, Sy-Yen Kuo, Colin Bolger:
IC HTOL Test Stress Condition Optimization. 272-279
Arvind Kumar, Sandip Tiwari:
Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics. 280-288
Carlos Arthur Lang Lisbôa, Luigi Carro:
Arithmetic Operators Robust to Multiple Simultaneous Upsets. 289-297
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. 298-305
Hung-Yau Lin, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo:
An Efficient Perfect Algorithm for Memory Repair Problems. 306-313
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy:
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. 314-315
Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi:
Error-Resilient Test Data Compression Using Tunstall Codes. 316-323
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
Online Testable Reversible Logic Circuit Design using NAND Blocks. 324-331
Nitin Parimi, Xiaoling Sun:
Toggle-Masking for Test-per-Scan VLSI Circuits. 332-338
Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui:
Learning Based on Fault Injection and Weight Restriction for Fault-Tolerant Hopfield Neural Networks. 339-346
John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk:
Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories. 347-355
Shanrui Zhang, Minsu Choi, Nohpill Park:
Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme. 356-364

Error Detection and Correction

Michele Favalli:
Annotated Bit Flip Fault Model. 366-376
Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
At-Speed Functional Verification of Programmable Devices. 386-394
Yung-Yuan Chen, Kun-Feng Chen:
Incorporating Signature-Monitoring Technique in VLIW Processors. 395-402

System-on-Chip Test

Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an I-IP for In-Field SOC Test. 404-412
Gang Zeng, Hideo Ito:
Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. 413-421

Circuit and System Reliability and Dependability

Matteo Sonza Reorda, Massimo Violante:
On-Line Analysis and Perturbation of CAN Networks. 424-432
Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto, Luigi Pomante:
Reliable System Co-Design: The FIR Case Study. 433-441
T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer:
Reliability Modeling and Assurance of Clockless Wave Pipeline. 442-450
Régis Leveugle, D. Cimonnet, Abdelaziz Ammari:
System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. 451-458

Novel Test Approaches

Jennifer Dworak, James Wingfield, M. Ray Mercer:
A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. 460-468
Irith Pomeranz, Sudhakar M. Reddy:
Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. 469-476

FPGA and Reconfigurable Circuit

Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu:
An Application-Independent Delay Testing Methodology for Island-Style FPGA. 478-486
Andrzej Krasniewski:
Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs. 487-495
Masaru Fukushi, Susumu Horiguchi:
Reconfiguration Algorithm for Degradable Processor Arrays Based on Row and Column Rerouting. 496-504

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