10. DDECS 2007: Kraków, Poland

Invited Presentations

Session I: Design for Test & Defect Analysis

Session II: SOC Design & Test

Session III: Fault Analysis & Circuit Reliability

Session IV: FPGA-Based Design

Poster Session I

Session V: Memory Testing

Session VI: Logic Design

Poster Session II

Session VII: Fault Tolerance I

Session VIII: Analog & RF Design

Session IX: Fault Tolerance II

Poster Session III

Session X: Test Quality & Test Generation

Session XI: Model Checking & Debugging

Session XII: Analog & MEMS testing