ED&TC 1997: Paris, France

System Analysis Techniques and Applications

Sequential ATPG

Design and Design Methodology for Analog Circuits

Advances in Built-In Self-Test

Synthesis of Controllers

Microsystems Design I

Software Generation for Embedded Processors

Register Transfer Level Test Synthesis

BDDs and Formal Verification

Microsystems Design II

High Performance Architectures for Multimedia and Communication ASICs

Decision Diagrams and Diagnosis

Performance Modeling

Progress in IDDQ Test Technology

Architecture Exploration

Layout Design

Testability Solutions for Regular Structures

Data Converter Test Issues

Extensions and Acceleration of Discrete Event Simulation

Analog Design and Layout Tools

Power Modeling and Estimation

Formal Methods in Synthesis and Verification

Concurrent Checking

New Ideas in Scheduling

System Level Design Representation and Transformation

Diagnosis and Test Generation

Logic Synthesis for Low Power

System Design Methodologies

Testability at Different Abstraction Levels

Hardware and Software Tools for Analog and Mixed-Signal Test

Power Estimation and Modeling


maintained by Schloss Dagstuhl LZI at University of Trier