European Design and Test Conference (ED&TC '97), Paris, France, 17-20 March 1997.
System Analysis Techniques and Applications
Design and Design Methodology for Analog Circuits
Advances in Built-In Self-Test
Synthesis of Controllers
Microsystems Design I
Software Generation for Embedded Processors
Register Transfer Level Test Synthesis
BDDs and Formal Verification
Microsystems Design II
High Performance Architectures for Multimedia and Communication ASICs
Decision Diagrams and Diagnosis
Progress in IDDQ Test Technology
: Deep sub-micron IDDQ testing: issues and solutions.
Testability Solutions for Regular Structures
Data Converter Test Issues
Extensions and Acceleration of Discrete Event Simulation
Analog Design and Layout Tools
Power Modeling and Estimation
Formal Methods in Synthesis and Verification
New Ideas in Scheduling
System Level Design Representation and Transformation
Diagnosis and Test Generation
Logic Synthesis for Low Power
System Design Methodologies
, C. Amies
: Practical concurrent ASIC and system design and verification.
: A methodology for hardware architecture trade-off at different levels of abstraction.
Testability at Different Abstraction Levels
Hardware and Software Tools for Analog and Mixed-Signal Test
Power Estimation and Modeling
: Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections.