DATE 2008: Munich, Germany

• Pieter J. Mosterman, Don Orofino, Janos Sztipanovits, Ahmed Amine Jerraya, Wido Kruijtzer, Víctor Reyes, Christos G. Cassandras, Grant Martin:
  Automatically Realising Embedded Systems from High-Level Functional Models.
  
• Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer:
  Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems.
  
• Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle:
  System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.
  
• Diana Marculescu, Sani R. Nassif:
  Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level.
  
• Jerry Frenkil, Ken Choi, Kimiyoshi Usami:
  Power Gating for Ultra-low Leakage: Physics, Design, and Analysis.
  
• Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel:
  Heterogeneous System-level Specification Using SystemC.
  
• Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen:
  Power-Aware Testing and Test Strategies for Low Power Devices.
  
• David Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury:
  From Transistor to PLL - Analogue Design and EDA Methods.
  
• Carsten Elgert, Volker Herbig, Anton Ossner, Thomas Harms, Emmanuel Blanc:
  DfM in the Analogue and Digital World.
  
• Rolf Ernst, Marek Jersak, Hans Sarnowski, Marco Bekooij, Samarjit Chakraborty:
  Formal Methods in System and MpSoC Performance Analysis and Optimisation.
  
• Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda:
  Soft Errors: System Effects, Protection Techniques and Case Studies.
  

• Giovanni De Micheli:
  Designing Micro/Nano Systems for a Safer and Healthier Tomorrow. 1
  
• Dominique Vernay:
  Perspective on Embedded Systems: Challenges, Solutions and Research Priorities. 2
  
• Yonghyun Hwang, Samar Abdi, Daniel Gajski:
  Cycle-approximate Retargetable Performance Estimation at the Transaction Level. 3-8
  
• Jérôme Cornet, Florence Maraninchi, Laurent Maillet-Contoz:
  A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip. 9-14
  
• Nicola Bombieri, Nicola Deganello, Franco Fummi:
  Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation. 15-20
  
• Walter Fuß:
  Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail Traffic. 21-25
  
• Jan B. Freuer, Göran Jerke, Joachim Gerlach, Wolfgang Nebel:
  On the Verification of High-Order Constraint Compliance in IC Design. 26-31
  
• Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli, Emmanuel Vaumorin:
  Industrial IP Integration Flows based on IP-XACT Standards. 32-37
  
• Timo Vogt, Norbert Wehn:
  A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment. 38-43
  
• Ben Cope, Peter Y. K. Cheung, Wayne Luk:
  Using Reconfigurable Logic to Optimise GPU Memory Accesses. 44-49
  
• Katarina Paulsson, Michael Hübner, Jürgen Becker:
  Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. 50-55
  
• Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll:
  Design flow for embedded FPGAs based on a flexible architecture template. 56-61
  
• A. Tchegho, Heinz Mattes, Sebastian Sattler:
  Optimal High-Resolution Spectral Analyzer. 62-67
  
• Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir:
  A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. 68-73
  
• Amir Zjajo, José Pineda de Gyvez:
  Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. 74-79
  
• Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda:
  Practical Implementation of a Network Analyzer for Analog BIST Applications. 80-85
  
• Joost-Pieter Katoen:
  Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques. 86-87
  
• Nicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, Meriem Zidouni:
  Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures. 88-89
  
• Lucia Cloth, Boudewijn R. Haverkort:
  Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices. 90-91
  
• Ying Tan, Qinru Qiu:
  A Framework of Stochastic Power Management Using Hidden Markov Model. 92-97
  
• Yu Zhou, Somnath Paul, Swarup Bhunia:
  Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. 98-103
  
• Davide Brunelli, Luca Benini, Clemens Moser, Lothar Thiele:
  An Efficient Solar Energy Harvester for Wireless Sensor Nodes. 104-109
  
• Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Luca Benini, Giovanni De Micheli:
  Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. 110-115
  
• Amir Hossein Ghamarian, Marc Geilen, Twan Basten, Sander Stuijk:
  Parametric Throughput Analysis of Synchronous Data Flow Graphs. 116-121
  
• Gunar Schirner, Rainer Dömer:
  Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling. 122-127
  
• Kim Grüttner, Frank Oppenheimer, Wolfgang Nebel, Fabien Colas-Bigey, Anne-Marie Fouilliart:
  SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder. 128-133
  
• Michel Vasilevski, François Pêcheux, Nicolas Beilleau, Hassan Aboushady, Karsten Einwich:
  Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN. 134-139
  
• Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
  Sizing Rules for Bipolar Analog Circuit Design. 140-145
  
• Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi:
  Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density. 146-151
  
• Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew D. Brown:
  A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits. 152-157
  
• Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich:
  Symbolic Reliability Analysis and Optimization of ECU Networks. 158-163
  
• Djones Lettnin, Pradeep Kumar Nalla, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Tobias Kirsten, Volker Schönknecht, Stephan Reitemeyer:
  Verification of Temporal Properties in Automotive Embedded Software. 164-169
  
• Bernd Stube, Bernd Schröder, Eckart Hoene, Andre Lissner:
  A Novel Approach for EMI Design of Power Electronics. 170-175
  
• Nicolas Alt, Christopher Claus, Walter Stechele:
  Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. 176-181
  
• Ozgur Sinanoglu, Erik Jan Marinissen:
  Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. 182-187
  
• Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng:
  Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. 188-193
  
• Paolo Bernardi, Matteo Sonza Reorda:
  An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. 194-199
  
• Jelte Peter Vink, Kees van Berkel, Pieter van der Wolf:
  Performance Analysis of SoC Architectures Based on Latency-Rate Servers. 200-205
  
• Sujan Pandey, Rolf Drechsler:
  Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. 206-211
  
• Philip K. F. Hölzenspies, Johann Hurink, Jan Kuper, Gerard J. M. Smit:
  Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC). 212-217
  
• Sungchan Kim, Chanik Park, Soonhoi Ha:
  Architecture Exploration of NAND Flash-based Multimedia Card. 218-223
  
• Hwisung Jung, Massoud Pedram:
  Resilient Dynamic Power Management under Uncertainty. 224-229
  
• Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini:
  Robust and Low Complexity Rate Control for Solar Powered Sensors. 230-235
  
• Shaobo Liu, Qinru Qiu, Qing Wu:
  Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting. 236-241
  
• Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, Taehwan Kim:
  Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution. 242-247
  
• Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu:
  Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs. 288-293
  
• Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran:
  A Formal Approach To The Protocol Converter Problem. 294-299
  
• Arno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen:
  Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip. 300-305
  
• Greg Hoover, Forrest Brewer:
  Synthesizing Synchronous Elastic Flow Networks. 306-311
  
• Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
  Periodic Steady-State Analysis Augmented with Design Equality Constraints. 312-317
  
• Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney, Kiran K. Gullapalli:
  Analysis of Oscillator Injection Locking by Harmonic Balance Method. 318-323
  
• Sebastian Steinhorst, Lars Hedrich:
  Model Checking of Analog Systems using an Analog Specification Language. 324-329
  
• Grégory Gailliard, Hugues Balp, Michel Sarlotte, François Verdier:
  Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components. 330-335
  
• Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, Hipólito Guzmán-Miranda:
  On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications. 336-341
  
• Massimiliano Melani, Lorenzo Bertini, Marco De Marinis, Peter Lange, Francesco D'Ascoli, Luca Fanucci:
  Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring. 342-347
  
• Drew C. Ness, David J. Lilja:
  Guiding Circuit Level Fault-Tolerance Design with Statistical Methods. 348-353
  
• Charu Nagpal, Rajesh Garg, Sunil P. Khatri:
  A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. 354-359
  
• Wenjing Rao, Alex Orailoglu:
  Towards fault tolerant parallel prefix adders in nanoelectronic systems. 360-365
  
• Swaroop Ghosh, Patrick Ndai, Kaushik Roy:
  A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. 366-371
  
• Jan Beutel, M. Beigl, Adam Dunkels, Koen Langendoen:
  Embedded Tutorial - Software for Wireless Networked Embedded Systems. 372
  
• Lawrence Leinweber, Swarup Bhunia:
  Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. 373-378
  
• Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
  A Scalable Algorithmic Framework for Row-Based Power-Gating. 379-384
  
• Ehsan Pakbaznia, Massoud Pedram:
  Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting. 385-390
  
• T. Forest, Alberto Ferrari, G. Audisio, Marco Sabatini, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale:
  Physical Architectures of Automotive Systems. 391-395
  
• Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
  A Mutation Model for the SystemC TLM 2.0 Communication Interfaces. 396-401
  
• Weixin Wu, Michael S. Hsiao:
  Efficient Design Validation Based on Cultural Algorithms. 402-407
  
• João Marques-Silva, Jordi Planes:
  Algorithms for Maximum Satisfiability using Unsatisfiable Cores. 408-413
  
• Shan Tang, Qiang Xu:
  In-band Cross-Trigger Event Transmission for Transaction-Based Debug. 414-419
  
• João M. S. Silva, Joel R. Phillips, Luis Miguel Silveira:
  Efficient Representation and Analysis of Power Grids. 420-425
  
• Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
  High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. 426-431
  
• Duo Li, Sheldon X.-D. Tan, Bruce McGaughy:
  ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis. 432-437
  
• Basel Halak, Alexandre Yakovlev:
  Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods. 438-443
  
• Min Li, Bruno Bougard, Weiyu Xu, David Novo, Liesbet Van der Perre, Francky Catthoor:
  Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures. 444-449
  
• Akash Kumar, Kees van Berkel:
  Vectorization of Reed Solomon Decoding and Mapping on the EVP. 450-455
  
• Matthias May, Matthias Alles, Norbert Wehn:
  A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder. 456-461
  
• Anshuman Chandra, Felix Ng, Rohit Kapur:
  Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. 462-467
  
• Melanie Elm, Hans-Joachim Wunderlich:
  Scan Chain Organization for Embedded Diagnosis. 468-473
  
• Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros:
  State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores. 474-479
  
• Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi:
  Automated Testability Enhancements for Logic Brick Libraries. 480-485
  
• Alexandre David, Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen:
  A Game-Theoretic Approach to Real-Time System Testing. 486-491
  
• Jonas Rox, Rolf Ernst:
  Modeling Event Stream Hierarchies with Hierarchical Event Models. 492-497
  
• Luiza Gheorghe, Faouzi Bouchhima, Gabriela Nicolescu, Hanifa Boucheneb:
  Semantics for Model-Based Validation of Continuous/Discrete Systems. 498-503
  
• Lisane B. de Brisolara, Marcio F. da S. Oliveira, Ricardo Miotto Redin, Luís C. Lamb, Luigi Carro, Flávio Rech Wagner:
  Using UML as Front-end for Heterogeneous Software Code Generation Strategies. 504-509
  
• S. Turnoy, Peter Wintermayr, Robert C. Aitken, Rudy Lauwereins, J. Tracy Weed, V. Kiefer, J. Hartmann:
  Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm. 510
  
• Harald Heinecke, Werner Damm, Bernhard Josko, Alexander Metzner, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale:
  Software Components for Reliable Automotive Systems. 549-554
  
• Herbert Hanselmann:
  Model-Based-Design Is Nice But... 555
  
• Soheil Samii, Sergiu Rafiliu, Petru Eles, Zebo Peng:
  A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems. 556-561
  
• Bao Liu:
  Signal Probability Based Statistical Timing Analysis. 562-567
  
• Behnam Amelifard, Safar Hatami, Hanif Fatemi, Massoud Pedram:
  A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect. 568-573
  
• Amit Goel, Sarma B. K. Vrudhula:
  Current source based standard cell model for accurate signal integrity and timing analysis. 574-579
  
• Wangyang Zhang, Wenjian Yu, Zeyi Wang, Zhiping Yu, Rong Jiang, Jinjun Xiong:
  An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation. 580-585
  
• Jorge Fernandez Villena, Luis Miguel Silveira:
  SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction. 586-591
  
• Brian Cline, Kaviraj Chopra, David Blaauw, Andres Torres, Savithri Sundareswaran:
  Transistor-Specific Delay Modeling for SSTA. 592-597
  
• Min Li, David Novo, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor:
  Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications. 598-603
  
• Ralf König, Timo Stripf, Jürgen Becker:
  A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. 604-609
  
• Philippe Bonnot, Fabrice Lemonnier, Gilbert Edelin, Gerard Gaillat, Olivier Ruch, Pascal Gauget:
  Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA. 610-615
  
• Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu:
  On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. 616-621
  
• Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah, Peter A. Habitz:
  Optimal Margin Computation for At-Speed Test. 622-627
  
• Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker:
  Resistive Bridging Fault Simulation of Industrial Circuits. 628-633
  
• Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D. Blanton:
  Physically-Aware N-Detect Test Pattern Selection. 634-639
  
• Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit:
  Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication. 640-645
  
• Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian:
  Constraint Refinement for Online Verifiable Cross-Layer System Adaptation. 646-651
  
• Parth Malani, Prakash Mukre, Qinru Qiu, Qing Wu:
  Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload. 652-657
  
• E. Schutz, K. Glinos, D. Beenaert, L. Gide:
  Embedded Tutorial - ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe. 658
  
• E. Frank, Reinhard Wilhelm, Rolf Ernst, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale:
  Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures. 659-663
  
• Stephen Plaza, Igor L. Markov, Valeria Bertacco:
  Random Stimulus Generation using Entropy and XOR Constraints. 664-669
  
• Ilya Wagner, Valeria Bertacco:
  MCjammer: Adaptive Verification for Multi-core Designs. 670-675
  
• Patrice Gerin, Xavier Guerin, Frédéric Pétrot:
  Efficient Implementation of Native Software Simulation for MPSoC. 676-681
  
• Xueqi Cheng, Michael S. Hsiao:
  Simulation-Directed Invariant Mining for Software Verification. 682-687
  
• Massoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner:
  Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation. 688-693
  
• Shun Li, Hua Chen, Feng Zhou:
  A Novel Technique for Improving Temperature Independency of Ring-ADC. 694-697
  
• Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner:
  An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs. 698-703
  
• Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Stephen P. Beeby, Russel N. Torah:
  Integrated approach to energy harvester mixed technology modelling and performance optimisation. 704-709
  
• Wolfgang Eberle, Michaël Goffioul:
  A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers. 710-715
  
• Bruno Bougard, Bjorn De Sutter, Sebastien Rabou, David Novo, Osman Allam, Steven Dupont, Liesbet Van der Perre:
  A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio. 716-721
  
• David Novo, Bruno Bougard, Andy Lambrechts, Liesbet Van der Perre, Francky Catthoor:
  Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios. 722-727
  
• C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
  Test Strategies for Low Power Devices. 728-733
  
• Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli:
  Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures. 734-739
  
• Olivier Certner, Zheng Li, Pierre Palatin, Olivier Temam, Frederic Arzel, Nathalie Drach:
  A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs. 740-745
  
• Matin Hashemi, Soheil Ghiasi:
  Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis. 746-751
  
• Lars Bauer, Muhammad Shafique, Stephanie Kreutz, Jörg Henkel:
  Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set. 752-757
  
• Hai Lin, Yunsi Fei:
  Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency. 758-763
  
• I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung:
  Instruction Set Extension Exploration in Multiple-Issue Architecture. 764-769
  
• Talal Bonny, Jörg Henkel:
  Instruction Re-encoding Facilitating Dense Embedded Code. 770-775
  
• Alberto L. Sangiovanni-Vincentelli, Marco Di Natale, Scuola S. Anna, H. Hanselmann, Harald Heinecke, Amar Bouali, Hermann Kopetz, H. Fennel, Thomas Weber:
  Panel Session - The Future Car: Technology, Methods and Tools. 812
  
• Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo:
  Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. 813-818
  
• Kuntal Nanshi, Fabio Somenzi:
  Improved Visibility in One-to-Many Trace Concretization. 819-824
  
• Tamarah Arons, Elad Elster, Shlomit Ozer, Jonathan Shalev, Eli Singerman:
  Efficient Symbolic Simulation of Low Level Software. 825-830
  
• Malay K. Ganai, Aarti Gupta:
  Completeness in SMT-based BMC for Software Programs. 831-836
  
• Tilo Meister, Jens Lienig, Gisbert Thomke:
  Novel Pin Assignment Algorithms for Components with Very High Pin Counts. 837-842
  
• Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici:
  A Generic Standard Cell Design Methodology for Differential Circuit Styles. 843-848
  
• Ashutosh Chakraborty, Sean X. Shi, David Z. Pan:
  Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. 849-855
  
• Amith Singhee, Sonia Singhal, Rob A. Rutenbar:
  Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. 856-861
  
• Alonso Morgado, Rocio del Río, José Manuel de la Rosa:
  A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications. 862-867
  
• Markus Bingesser, Teddy Loeliger, Werner Hinn, Johann Hauer, Stefan Modl, Robert Dorn, Matthias Völker:
  Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement. 868-872
  
• Mustafa Badaroglu, Guy Decabooter, Francois Laulanet, Olivier Charlier:
  Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. 873-878
  
• Francesco D'Ascoli, Luca Bacciarelli, Massimiliano Melani, Luca Fanucci, G. Ricotti, E. Pardi, F. Vincis, Massimiliano Forliti, Marco De Marinis:
  A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology. 879-884
  
• Yanjing Li, Samy Makar, Subhasish Mitra:
  CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns. 885-890
  
• Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li:
  Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. 891-896
  
• Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche:
  A low-cost concurrent error detection technique for processor control logic. 897-902
  
• Mihir R. Choudhury, Kartik Mohanram:
  Approximate logic circuits for low overhead, non-intrusive concurrent error detection. 903-908
  
• Krishnendu Chatterjee, Arkadeb Ghosal, Thomas A. Henzinger, Daniel T. Iercan, Christoph M. Kirsch, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli:
  Logical Reliability of Interacting Real-Time Tasks. 909-914
  
• Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng:
  Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints. 915-920
  
• Jonas Elmqvist, Simin Nadjm-Tehrani:
  Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems. 921-927
  
• Jean-Pierre Talpin, Julien Ouy, Loïc Besnard, Paul Le Guernic:
  Compositional design of isochronous systems. 928-933
  
• Frank Badstubner, Andreas Vörg:
  Quantitative Productivity Measurement in IC Design. 934-935
  
• Peter Leppelt, Erich Barke:
  Determining the Technical Complexity of Integrated Circuits. 935
  
• Stefan Häusler, Frank Poppen, Kevin Hausmann, Axel Hahn, Wolfgang Nebel:
  Qalitative and Quantitative Analysis of IC Designs. 935-936
  
• Jonathan Young:
  Capturing and Analyzing IC Design Productivity Metrics. 936-937
  
• Katharina Weinberger, Slava Bulach, Robert Bosch:
  Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits. 937-938
  
• Hans-Jürgen Brand:
  Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations. 938-939
  
• Jacob A. Abraham:
  Implications of Technology Trends on System Dependability. 940
  
• Subhasish Mitra:
  Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges. 941-946
  
• Ute Wappler, Martin Muller:
  Software Protection Mechanisms for Dependable Systems. 947-952
  
• Marino Strik, Alain Gonier, Paul Williams:
  Subsystem Exchange in a Concurrent Design Process Environment. 953-958
  
• Raffaele Penazzi, Piergiorgio Capozio, Martin Duncan, Angelo Scuderi, Max Siti, Edoardo Merli:
  Cooperative Safety: a Combination of Multiple Technologies. 959-961
  
• Albrecht Mayer, Frank Hellwig:
  System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture. 962-966
  
• Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii:
  Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style. 967-972
  
• Andrea Calimera, Luca Benini, Enrico Macii:
  Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. 973-978
  
• Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri:
  A Single-supply True Voltage Level Shifter. 979-984
  
• Victor H. Cordero Calle, Sunil P. Khatri:
  Clock Distribution Scheme using Coplanar Transmission Lines. 985-990
  
• Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana:
  Compositional, dynamic cache management for embedded chip multiprocessors. 991-996
  
• Pierre Guironnet de Massas, Frédéric Pétrot:
  Comparison of memory write policies for NoC based Multicore Cache Coherent Systems. 997-1002
  
• Simon Ogg, Enrico Valli, Bashir M. Al-Hashimi, Alexandre Yakovlev, Crescenzo D'Alessandro, Luca Benini:
  Serialized Asynchronous Links for NoC. 1003-1008
  
• Jie Zhang, Nishant Patil, Subhasish Mitra:
  Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. 1009-1014
  
• Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große:
  Quantified Synthesis of Reversible Logic. 1015-1020
  
• Nicholas Allec, Robert G. Knobel, Li Shang:
  Adaptive Simulation for Single-Electron Devices. 1021-1026
  
• Francisco J. Rincón, Michele Paselli, Joaquín Recas, Qin Zhao, Marcos Sanchez-Elez, David Atienza, Julien Penders, Giovanni De Micheli:
  OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks. 1027-1032
  
• Alejandro Masrur, Sebastian Drössler, Georg Färber:
  Improvements in Polynomial-Time Feasibility Testing for EDF. 1033-1038
  
• Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
  A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. 1039-1044
  
• Claas Diederichs, Ulrich Margull, Frank Slomka, Gerhard Wirrer:
  An application-based EDF scheduler for OSEK/VDX. 1045-1050
  
• Gianluca Franchino, Giorgio C. Buttazzo, Tullio Facchinetti:
  Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme. 1051-1056
  
• Jason Cong, Junjuan Xu:
  Simultaneous FU and Register Binding Based on Network Flow Method. 1057-1062
  
• Feng Wang, Guangyu Sun, Yuan Xie:
  A Variation Aware High Level Synthesis Framework. 1063-1068
  
• Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov:
  EPIC: Ending Piracy of Integrated Circuits. 1069-1074
  
• Adeel Israr, Sorin A. Huss:
  Specification and Design Considerations for Reliable Embedded Systems. 1111-1116
  
• Petru Eles, Viacheslav Izosimov, Paul Pop, Zebo Peng:
  Synthesis of Fault-Tolerant Embedded Systems. 1117-1122
  
• Hermann Kopetz:
  Reliable Services in an Imperfect World. 1123
  
• Pieter van der Wolf, Tomas Henriksson:
  Video Processing Requirements on SoC Infrastructures. 1124-1125
  
• Dinesh Pamunuwa:
  Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. 1126-1127
  
• Nikil Dutt:
  Memory-aware NoC Exploration and Design. 1128-1129
  
• Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah:
  Incremental Criticality and Yield Gradients. 1130-1135
  
• Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan:
  Latch Modeling for Statistical Timing Analysis. 1136-1141
  
• Andrey Mokhov, Alexandre Yakovlev:
  Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis. 1142-1147
  
• Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar:
  Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. 1148-1153
  
• Xi Chen, Robert P. Dick, Alok N. Choudhary:
  Operating System Controlled Processor-Memory Bus Encryption. 1154-1159
  
• Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary:
  An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. 1160-1165
  
• Irith Pomeranz, Sudhakar M. Reddy:
  A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. 1166-1171
  
• Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad Tehranipoor:
  Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation. 1172-1177
  
• Shideh Shahidi, Sandeep Gupta:
  Multi-Vector Tests: A Path to Perfect Error-Rate Testing. 1178-1183
  
• Jia Li, Qiang Xu, Yu Hu, Xiaowei Li:
  iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. 1184-1189
  
• Sanghyun Park, Aviral Shrivastava, Yunheung Paek:
  Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors. 1190-1195
  
• Timothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O'Boyle:
  Instruction Cache Energy Saving Through Compiler Way-Placement. 1196-1201
  
• Chun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, Meikang Qiu:
  Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. 1202-1207
  
• Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro:
  Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications. 1208-1213
  
• Christophe Wolinski, Krzysztof Kuchcinski:
  Automatic Selection of Application-Specific Reconfigurable Processor Extensions. 1214-1219
  
• Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne Wolf:
  An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications. 1220-1225
  
• Ed Brinksma, Jozef Hooman:
  Dependability for high-tech systems: an industry-as-laboratory approach. 1226-1231
  
• Chen-Ling Chou, Radu Marculescu:
  User-Aware Dynamic Task Allocation in Networks-on-Chip. 1232-1237
  
• Mohammad Abdullah Al Faruque, Jörg Henkel:
  Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures. 1238-1243
  
• Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo:
  An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication. 1244-1249
  
• Ajay K. Verma, Philip Brisk, Paolo Ienne:
  Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. 1250-1255
  
• Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
  Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. 1256-1261
  
• Ivano Bonesana, Marco Paolieri, Marco D. Santambrogio:
  An adaptable FPGA-based System for Regular Expression Matching. 1262-1267
  
• Miroslav N. Velev, Ping Gao:
  Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems. 1268-1273
  
• Denis Réal, Cécile Canovas, Jessy Clédière, M'hamed Drissi, Frédéric Valette:
  Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis. 1274-1279
  
• Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin:
  Power Balanced Gates Insensitive to Routing Capacitance Mismatch. 1280-1285
  
• Elena Dubrova, Maxim Teslenko, Hannu Tenhunen:
  On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers. 1286-1291
  
• Junfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid Verbauwhede:
  FPGA Design for Algebraic Tori-Based Public-Key Cryptography. 1292-1297
  
• Ho Fai Ko, Nicola Nicolici:
  Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. 1298-1303
  
• Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis:
  Functional Self-Testing for Bus-Based Symmetric Multiprocessors. 1304-1309
  
• B. Straka, Hans A. R. Manhaeve, J. Brenkus, Stefaan Kerckenaere:
  Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality. 1310-1315
  
• Marcello De Matteis, Stefano D'Amico, Andrea Baschirotto:
  Advanced Analog Filters for Telecommunications. 1316-1321
  
• Georges G. E. Gielen, Peter H. N. De Wit, Elie Maricau, J. Loeckx, J. Martín-Martínez, Ben Kaczer, Guido Groeseneken, R. Rodríguez, M. Nafría:
  Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. 1322-1327
  
• Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici:
  Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. 1328-1333
  
• Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
  High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. 1334-1339
  
• Amin Farmahini Farahani, Seid Mehdi Fakhraie, Saeed Safari:
  Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence. 1340-1345
  
• Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev:
  Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems. 1346-1351
  
• Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, Philippe Millet, Matthias Kühnle, Florian Ries, Michael Hübner, Jürgen Becker, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco:
  Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. 1352-1357
  
• Neeraj Suri, Christof Fetzer, Jacob Abraham, Stefan Poledna, Avi Mendelson, Subhasish Mitra:
  Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems. 1394-1395
  
• Faizal Arya Samman, Thomas Hollstein, Manfred Glesner:
  Multicast Parallel Pipeline Router Architecture for Network-on-Chip. 1396-1401
  
• Simone Medardoni, Marcello Lajolo, Davide Bertozzi:
  Variation tolerant NoC design by means of self-calibrating links. 1402-1407
  
• Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi:
  BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. 1408-1413
  
• Igor Loi, Federico Angiolini, Luca Benini:
  Developing Mesochronous Synchronizers to Enable 3D NoCs. 1414-1419
  
• Arseni Vitkovski, Georgi Kuzmanov, Georgi Gaydadjiev:
  Memory Organization with Multi-Pattern Parallel Accesses. 1420-1425
  
• Marios Kleanthous, Yiannakis Sazeides:
  CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches. 1426-1431
  
• Sukhun Kang, Rakesh Kumar:
  Magellan: A Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization. 1432-1437
  
• Raghavendra K, Madhu Mutyam:
  Process Variation Aware Issue Queue Design. 1438-1443
  
• Claudio Mucci, Luca Vanzolini, Ilario Mirimin, Daniele Gazzola, Antonio Deledda, Sebastian Goller, Joachim Knäblein, Axel Schneider, Luca Ciccarelli, Fabio Campi:
  Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array. 1444-1449
  
• R. Arteaga, Félix Tobajas, Roberto Esper-Chaín, V. de Armas, Roberto Sarmiento:
  GMDS: Hardware implementation of novel real output queuing architecture. 1450-1455
  
• Jeremy Buboltz, Taskin Koçak:
  Front End Device for Content Networking. 1456-1461
  
• Madhura Purnaprajna, Christoph Puttmann, Mario Porrmann:
  Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. 1462-1467
  
• Hyun Choi, Abhijit Chatterjee:
  Digital bit stream jitter testing using jitter expansion. 1468-1473
  
• Irith Pomeranz, Sudhakar M. Reddy:
  A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. 1474-1479
  
• Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
  A Design-for-Diagnosis Technique for SRAM Write Drivers. 1480-1485
  
• David C. Keezer, Dany Minier, Patrice Ducharme:
  Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications. 1486-1491
  
• Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh:
  Retargetable Code Optimization for Predicated Execution. 1492-1497
  
• Stephen A. Edwards, Nalini Vasudevan, Olivier Tardieu:
  Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads. 1498-1503
  
• Roberto Lublinerman, Stavros Tripakis:
  Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams. 1504-1509
  
• Fabiano Cruz, Raimundo S. Barreto, Lucas Cordeiro, Paulo Romero Martins Maciel:
  ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis. 1510-1515
  
• Bruno Bougard, Paul Marchal, Luca Benini, Doris Keitel-Schulz, N. Checka:
  HOT TOPIC - 3D Integration or How to Scale in the 21st Century. 1516
  
• Atanu Chattopadhyay, Zeljko Zilic:
  Built-in Clock Skew System for On-line Debug and Repair. 248-251
  
• Renato Rimolo-Donadio, Christian Schuster, Xiaoxiong Gu, Young Hoon Kwark, Mark B. Ritter:
  Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects. 252-255
  
• Ho Fai Ko, Nicola Nicolici:
  On Automated Trigger Event Generation in Post-Silicon Validation. 256-259
  
• Ken W. Batcher, Robert A. Walker:
  Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems. 260-263
  
• Yang Qu, Juha-Pekka Soininen, Jari Nurmi:
  Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking. 264-267
  
• Mian Dong, Lin Zhong:
  Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration. 268-271
  
• Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis:
  Merged Computation for Whirlpool Hashing. 272-275
  
• Trevor Meyerowitz, Alberto L. Sangiovanni-Vincentelli, Mirko Sauermann, Dominik Langen:
  Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor. 276-279
  
• Juan Alberto Herreria Garcia:
  Safe Automatic Flight Back and Landing of Aircraft Flight Reconfiguration Function (FRF). 280-283
  
• Daniela De Venuto, Leonardo Reyneri:
  PWM-Based Test Stimuli Generation for BIST of High Resolution ADCs. 284-287
  
• Jan Schat:
  Fault Clustering in deep-submicron CMOS Processes. 511-514
  
• Chunjie Duan, Sunil P. Khatri:
  Energy Efficient and High Speed On-Chip Ternary Bus. 515-518
  
• Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto:
  Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems. 519-522
  
• Almitra Pradhan, Ranga Vemuri:
  Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. 523-526
  
• Bao Liu:
  Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. 527-532
  
• Mohamed El Mongi Ben Gaid, Rémy Kocik, Yves Sorel, Rédha Hamouche:
  A methodology for improving software design lifecycle in embedded control systems. 533-536
  
• Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng:
  Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. 537-540
  
• Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker:
  A System Architecture for Reconfigurable Trusted Platforms. 541-544
  
• Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke:
  Automatic Generation of Complex Properties for Hardware Designs. 545-548
  
• Martin Versen, Achim Schramm, Jan Schnepp, Dorina Diaconescu:
  Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices. 776-779
  
• Bastian Ristau, Torsten Limberg, Gerhard Fettweis:
  A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs. 780-783
  
• Josef Haid, Bernd Zimek, Thomas Leutgeb, Thomas Kunemund:
  Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication. 784-787
  
• Martin Radetzki, Rauf Salimi Khaligh:
  Accuracy-Adaptive Simulation of Transaction Level Models. 788-791
  
• Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang:
  Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor. 792-795
  
• Fu-Wei Chen, Yi-Yu Liu:
  Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. 796-799
  
• Xiaoying Wang, Lars Hedrich:
  Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. 800-803
  
• Alexandre Lewicki, Javier del Prado Pavon, Jacky Talayssat, Eric Dekneuvel, Gilles Jacquemod:
  A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design. 804-807
  
• Feng Yuan, Lin Huang, Qiang Xu:
  Re-Examining the Use of Network-on-Chip as Test Access Mechanism. 808-811
  
• Simone Zezza, Guido Masera:
  VLSI implementation of SISO arithmetic decoders for joint source channel coding. 1075-1078
  
• Stephen Frechette, Fabrizio Lombardi:
  Error Detection/Correction in DNA Algorithmic Self-Assembly. 1079-1082
  
• Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng:
  Temperature-Aware Voltage Selection for Energy Optimization. 1083-1086
  
• Lei Fang, Michael S. Hsiao:
  A Fast Approximation Algorithm for MIN-ONE SAT. 1087-1090
  
• Jun-Kuei Zeng, Chung-Ping Chen:
  Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis. 1091-1094
  
• Yi Lu, Thomas Marconi, Georgi Gaydadjiev, Koen Bertels:
  An efficient algorithm for free resources management on the FPGA. 1095-1098
  
• Hiroaki Yoshida, Masahiro Fujita:
  Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. 1099-1102
  
• Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz:
  Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. 1103-1106
  
• Patrick Scheer, Ernst Schmidt, Stefan Burges:
  CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive Applications. 1107-1110
  
• Mark Muir, Tughrul Arslan, Iain Lindsay:
  Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications. 1358-1361
  
• Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty:
  Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. 1362-1365
  
• Tomokazu Yoneda, Hideo Fujiwara:
  Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. 1366-1369
  
• Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
  De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. 1370-1373
  
• Lan S. Bai, Haris Lekatsas, Robert P. Dick:
  Adaptive Filesystem Compression for Embedded Systems. 1374-1377
  
• David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
  Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. 1378-1381
  
• Per Lindgren, Johan Eriksson, Simon Aittamaa, Johan Nordlander:
  TinyTimber, Reactive Objects in C for Real-Time Embedded Systems. 1382-1385
  
• Eduardo Wenzel Brião, Daniel Barcelos, Flávio Rech Wagner:
  Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications. 1386-1389
  
• Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas:
  Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. 1390-1393
  

Last update Wed Feb 15 04:59:00 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page