DATE 2006: Munich, Germany

Keynote Addresses

Allocation and scheduling for MPSoCs and NoCs

Power grid and large interconnect network analysis

Interactive presentation

On-line testing and fault tolerance

Interactive presentation

Chip design records

Model based design and test

Transaction level modelling based validation

Application-specific network on chip design

Interactive presentation

Methods and tools for systematic analogue design

Interactive presentation

Soft error analysis and concurrent testing

System design records

Application-specific architectures

System level performance analysis

Hot topic - 'Network': the Next 'Big Idea' in design? network paradigms in systems, sensors, and silicon

Advances in verification and synthesis for analogue design automation

Interactive presentation

Advanced SoC test scheduling

Interactive presentation

Design methodologies for emerging technologies

Interactive presentation

Processor and memory design

Spatial and temporal mapping for reconfigurable computing

DFM/DFY design for manufacturability and yield

Analogue and mixed-signal design

Interactive presentation

Processor self-test and fault diagnosis

Interactive presentation

Scheduling for real-time and energy

System level modelling and simulation

Interactive presentation

Hot topic: system level design of SoC (4G wireless special day)

Power-efficient hardware/software architectures

Interactive presentation

Timing and noise analysis

Interactive presentation

Test and reliability challenges in automotive microelectronics

Communication methods and networking in automotive systems

System level modelling

Interactive presentation

Hot topic: architectures and NoC (4G wireles special day)

Keynote

Low power embedded architectures and platforms

Interactive presentation

Transistor and gate level simulation

Interactive presentation

SoC targeted mixed-signal test solutions