DATE 2005:
Munich, Germany
Volume 1
Keynote Addresses
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Garry Hughes :
Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges.
3
1A:
Partitioning and Optimisation for Reconfigurable Computing
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Roman L. Lysecky ,
Frank Vahid :
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.
18-23
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Interactive Presentations
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1B:
Hot Topic - Analogue/Digital Circuit Design in 65nm:
End of the Road
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1C:
SoC Design-for-Test
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Interactive Presentation
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1E:
Embedded Tutorial - Cross-Pollination between HW and SW - Hard Lessons for Software, and Vice Versa
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Alexander G. Dean :
Software Thread Integration and Synthesis for Real-Time Applications.
68-69
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Ian Oliver :
Applying UML and MDA to Real Systems Design.
70-71
1F:
Low Power Design with Error Tolerance
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2A:
Scheduling and Synthesis for Reconfigurable Computin
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2B:
Analogue Simulation, Placement and Statistical Analysis
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Ewout Martens ,
Georges G. E. Gielen :
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series.
120-125
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2C:
Analogue and Gigahertz Test
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Interactive Presentations
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2E:
Ubiquitous Computing:
Security and Energy Aspects
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Arijit Ghosh ,
Tony Givargis :
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks.
190-195
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Interactive Presentation
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2F:
Power Aware Design in DSM Technology
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conf/date/MukhopadhyayBR05
Interactive Presentation
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3A:
Reconfigurability in MPSoC
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Interactive Presentation
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3B:
Analogue, Mixed-Signal and RF Circuits and Systems
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Hua Tang ,
Ying Wei ,
Alex Doboli :
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption.
264-269
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Interactive Presentations
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3C:
Reliability at the Very Deep Sub-Micron Region
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conf/date/KrishnaswamyVMH05 export record as
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Osama Neiroukh ,
Xiaoyu Song :
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques.
294-299
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Interactive Presentations
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conf/date/Lopez-OngilGPE05
3F:
HW/SW Solutions for Low Power Multimedia Systems
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Arne Hamann ,
Rolf Ernst :
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques.
312-317
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conf/date/Abdel-HamidTA05
Interactive Presentation
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Philippe Martin :
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer.
336-337
3F:
HW/SW Solutions for Low Power Multimedia Systems
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Ümit Y. Ogras ,
Radu Marculescu :
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach.
352-357
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Tohru Ishihara ,
Farzan Fallah :
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors.
358-363
4A:
Embedded System Partitioning and Validation
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Interactive Presentation
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Greg Stitt ,
Frank Vahid :
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms.
396-397
4B:
Logic Synthesis
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conf/date/MishchenkoBJVY05 export record as
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Interactive Presentations
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4C:
Defect Detection and Characterisation
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Interactive Presentations
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4E:
Real-Time Scheduling
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Rafik Henia ,
Rolf Ernst :
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies.
480-485
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Interactive Presentation
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4F:
SoC Power Optimisation
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Mirko Loghi ,
Massimo Poncino :
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions.
508-513
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Interactive Presentations
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4G:
Embedded Tutorial - Platforms and Tools for Automotive System Design
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conf/date/Sangiovanni-Vincentelli05 export record as
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Thomas Illgen ,
Stefan Ortmann :
Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective.
536-537
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5A:
System Level Languages, Verification and Simulation
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Interactive Presentations
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Wolfgang Klingauf :
Systematic Transaction Level Modeling of Embedded Systems with SystemC.
566-567
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5B:
Panel Session - Semiconductor Industry Disaggregation vs. Reaggregation:
Who will be the Shark?
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5C:
Reliable Memory Design
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5E:
Execution-Time Analysis
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Interactive Presentations
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5F:
Battery and Current Considerations in CMOS Design
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Jawad Khan ,
Ranga Vemuri :
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms.
622-627
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Interactive Presentations
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5G:
Panel Session - Automotive System Architectures
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conf/date/BortolazziMBM05
5K:
Keynote
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Harald Heinecke :
Automotive System Design - Challenges and Potential.
656-657
Volume 2
6A:
High-Level Verification
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Interactive Presentations
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6B:
System Modelling with UML
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conf/date/SchattkowskyMR05 export record as
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Interactive Presentations
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conf/date/VanderperrenD05 export record as
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6C:
Hot Topic - Challenges in Embedded Memory Design and Test
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conf/date/MarinissenPKZ05
6E:
Parallel and Multithreaded Processor Architectures
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Interactive Presentation
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6F:
Very Deep Submicron Simulation
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Zhao Li ,
C.-J. Richard Shi :
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.
752-757
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Interactive Presentation
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6G:
SoC Prototyping and Simulation
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conf/date/MahadevanASOSM05 export record as
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Interactive Presentation
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7A:
Memory Optimisation and Clocking for SoC
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Interactive Presentations
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7B:
Embedded Tutorial - UML for System-on-Chip Design:
Current Applications and Future Perspectives
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7C:
Test Power Reduction and Diagnosis
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Interactive Presentations
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conf/date/CheonLWWHCPCW05
7E:
Scheduling and Memory Optimisation for Multiprocessor Embedded Systems
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Interactive Presentations
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7F:
Layout Issues
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Interactive Presentations
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conf/date/AlexandreCCSME05 export record as
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Amitava Bhaduri ,
Ranga Vemuri :
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric.
922-923
7G:
Quantifying Architecture Trade-Off
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Interactive Presentations
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conf/date/DasygenisBDCST05
8A:
Panel Session - Is There a Market for SystemC Tools?
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conf/date/RosenstielBGGKLMMMS05
8B:
Interconnect Solutions:
Timing, Noise, and Process Variations
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Baohua Wang ,
Pinaki Mazumder :
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation.
976-981
Interactive Presentations
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Ajith Chandy ,
Tom Chen :
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions.
984-985
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8C:
Advances in Pattern Generation for Fault Detection and Diagnosis
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conf/date/ChandrasekarH05 export record as
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Interactive Presentations
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8E:
Embedded Software Technology
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conf/date/BaleaniFMSFSW05 export record as
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Interactive Presentations
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Tadashi Takeuchi :
OS Debugging Method Using a Lightweight Virtual Machine Monitor.
1058-1059
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8F:
Advanced Analogue Performance Modelling
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conf/date/VandersteenLJRP05 export record as
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Interactive Presentation
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8G:
Hot Topic - Biochips:
Principles and Application
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conf/date/ManaresiMAAVRATG05
9A:
Efficient SAT Based Verification
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9B:
Embedded Tutorial - How Do They Manage Designing Complex SoC?
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Cheng-Wen Wu :
SOC Testing Methodology and Practice.
1120-1121
9C:
Test Pattern Compression and Delay Test Schemes
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conf/date/BalakrishnanT05 export record as
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9E:
Compiler/Architecture Codesign
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Elena Dubrova :
Structural Testing Based on Minimum Kernels.
1168-1173
9F:
Network-on-Chip Design Flows
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conf/date/GoossensDGPRR05 export record as
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conf/date/StergiouACRBM05
9G:
Biochips and Quantum Computing
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9K:
CMOS-Based Biosensor Arrarys
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conf/date/ThewesPSHFBAJESAHBHH05 Roland Thewes ,
Christian Paulus ,
Meinrad Schienle ,
Franz Hofmann ,
Alexander Frey ,
Ralf Brederlow ,
M. Augustyniak ,
Martin Jenkner ,
Björn Eversmann ,
Petra Schindler-Bauer ,
Melanie Atzesberger ,
Birgit Holzapfl ,
Gottfried Beer ,
Thomas Haneder ,
Hans-Christian Hanke :
CMOS-Based Biosensor Arrays.
1222-1223
10A:
Efficient Network-on-Chip Architectures
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Tobias Bjerregaard ,
Jens Sparsø :
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip.
1226-1231
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10B:
Architectural Synthesis and Design Space Exploration
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conf/date/Ruiz-SautuaMMH05 export record as
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conf/date/ShrivastavaDNE05
10C:
Concurrent Error Detection and Correction
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conf/date/KastensmidtSCR05
10E:
Formal Verification of Processor Architecture and DSP Programs
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conf/date/ShashidharBCJ05
10F:
Interconnect Optimisation
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Zhuo Li ,
Weiping Shi :
An O(bn2 ) Time Algorithm for Optimal Buffer Insertion with b Buffer Types.
1324-1329
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10G:
Hot Topic - Silicon Based Biochips
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Raymond Campagnolo :
eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection.
1338-1339
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conf/date/KirsteinLZVVSLH05
Volume 3
1D:
Media and Signal Processing
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Sandro V. Silva ,
Sergio Bampi :
Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures.
32-37
2D:
Secure and Embedded Security Systems
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Zoya Dyka ,
Peter Langendoerfer :
Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method.
70-75
Interactive Presentations
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Hala A. Farouk ,
Magdy Saeb :
An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security.
76-81
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3D:
Hot Topic - MPSoC Platforms for Mobile Multimedia
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Wayne Wolf :
Multimedia Applications of Multiprocessor Systems-on-Chips.
86-89
4D:
Hot Topic - Low-Power Wireless LANs:
Past, Present and Future
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Keith Holt :
Wireless LAN: Past, Present, and Future.
92-93
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conf/date/BlazquezLWGPC05 export record as
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5D:
Wireless Communication and Networking
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conf/date/PapaefstathiouOKKMN05 export record as
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Interactive Presentations
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6D:
Automotive
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Wayne Lyons :
Meeting the Embedded Design Needs of Automotive Applications.
142-147
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Pavel Horsky :
LC Oscillator Driver for Safety Critical Applications.
159-164
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conf/date/StaschulatESW05 export record as
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conf/date/ZiegenbeinBFBRS05
Interactive Presentation
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Massimo Conti :
SystemC Analysis of a New Dynamic Power Management Architectur.
177-178
7D:
Sensors
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conf/date/ChappellMPOFS05 export record as
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Momchil Milev ,
Rod Burt :
A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems.
204-208
8D:
Best of ESSCIRC 2004
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conf/date/KirsteinSSHVH04 export record as
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conf/date/AndersenBTBBHM04 export record as
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9D:
IP-Reuse and Reconfigurable Systems
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Dan Hillman :
Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm.
240-246
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10D:
Design Verification
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conf/date/BorgattiCRLMFP04 export record as
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