DATE 2005: Munich, Germany

Volume 1

Keynote Addresses

1A: Partitioning and Optimisation for Reconfigurable Computing

Interactive Presentations

1B: Hot Topic - Analogue/Digital Circuit Design in 65nm: End of the Road

1C: SoC Design-for-Test

Interactive Presentation

1E: Embedded Tutorial - Cross-Pollination between HW and SW - Hard Lessons for Software, and Vice Versa

1F: Low Power Design with Error Tolerance

2A: Scheduling and Synthesis for Reconfigurable Computin

2B: Analogue Simulation, Placement and Statistical Analysis

2C: Analogue and Gigahertz Test

Interactive Presentations

2E: Ubiquitous Computing: Security and Energy Aspects

Interactive Presentation

2F: Power Aware Design in DSM Technology

Interactive Presentation

3A: Reconfigurability in MPSoC

Interactive Presentation

3B: Analogue, Mixed-Signal and RF Circuits and Systems

Interactive Presentations

3C: Reliability at the Very Deep Sub-Micron Region

Interactive Presentations

3F: HW/SW Solutions for Low Power Multimedia Systems

Interactive Presentation

3F: HW/SW Solutions for Low Power Multimedia Systems

4A: Embedded System Partitioning and Validation

Interactive Presentation

4B: Logic Synthesis

Interactive Presentations

4C: Defect Detection and Characterisation

Interactive Presentations

4E: Real-Time Scheduling

Interactive Presentation

4F: SoC Power Optimisation

Interactive Presentations

4G: Embedded Tutorial - Platforms and Tools for Automotive System Design

5A: System Level Languages, Verification and Simulation

Interactive Presentations

5B: Panel Session - Semiconductor Industry Disaggregation vs. Reaggregation: Who will be the Shark?

5C: Reliable Memory Design

5E: Execution-Time Analysis

Interactive Presentations

5F: Battery and Current Considerations in CMOS Design

Interactive Presentations

5G: Panel Session - Automotive System Architectures

5K: Keynote

Volume 2

6A: High-Level Verification

Interactive Presentations

6B: System Modelling with UML