2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France.
IEEE Computer Society 2004, ISBN 0-7695-2085-5 Volume 1 - 2 - Designers Forum
Performances Analysis for MPSoC
Synthesis for Noise and Manufacturability
Support for BIST
Modelling, Simulation and Optimisation in Power/Ground/Substrate
Panel Session - Chips of the Future:
Soft, Crunchy or Hard?
Pierre G. Paulin
: DATE Panel: Chips of the Future: Soft, Crunchy or Hard?
Power-Aware Networks and Interfaces
Networks on Chip Design
Advances in Technology Mapping and Circuit Sizing
Panel Session - Nanometer Design - What are the Requirements for Manufacturing Test?
Issues in Interconnect Simulation and Model Order Reduction
: Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals.
From Sensors to Qubits
Embedded Tutorial - Architectures and Design Techniques for Energy-Efficient Embedded DSP and Multimedia Processing
Platform-Based Design and VC Reuse Methods
Real-Time Issues in Embedded Systems
Real-Life Defect Modelling and Detection
Optimisation in Physical Design
, Hai Zhou
: Wire Retiming for System-on-Chip by Fixpoint Computation.
, Lei He
: Full-Chip Multilevel Routing for Power and Signal Integrity.
Hot Topic - Platforms and Tools for Energy-Efficient Design of Multimedia Systems
Communication Design for MPSoC
Combining Static and Dynamic Software Optimisation
Hot Topic - The Status of the New IEEE Test Standards
Modelling and Estimation in Circuit Layout
Applications of Reconfigurability
: Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience.
Interconnect Modelling for MPSoC
Embedded Software Generation and Optimisation
Novel Approaches to Analogue Simulation
, C.-J. Richard Shi
: Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation.
Embedded Tutorial - System Verilog for VHDL Users
Hot Topic - Quo Vadis Multimedia? From Desktop Multimedia to Distributed Multimedia Systems
: A Demonstration of Co-Design and Co-Verification in a Synchronous Language.