Performances Analysis for MPSoC

• 
  Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon: Analyzing On-Chip Communication in a MPSoC Environment. 752-757
• 
  Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert: A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC. 758-763
• 
  Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach. 764-769
• 
  Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv: A Case Study in Networks-on-Chip Design for Embedded Video. 770-777

Synthesis for Noise and Manufacturability

• 
  Chunjie Duan, Sunil P. Khatri: Exploiting Crosstalk to Speed up On-Chip Buse. 778-783
• 
  Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer: False-Noise Analysis for Domino Circuits. 784-789
• 
  Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang: Crosstalk Minimization in Logic Synthesis for PLA. 790-795
• 
  Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli: Synthesis for Manufacturability: A Sanity Check. 796-803

Support for BIST

• 
  M. Amir Abas, Gordon Russell, D. J. Kinniment: Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit. 804-809
• 
  Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich: Impact of Test Point Insertion on Silicon Area and Timing during Layout. 810-815
• 
  Hani Rizk, Christos A. Papachristou, Francis G. Wolff: Designing Self Test Programs for Embedded DSP Cores. 816-823

Modelling, Simulation and Optimisation in Power/Ground/Substrate

• 
  Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury: Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. 824-829
• 
  Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen: Thermal and Power Integrity Based Power/Ground Networks Optimization. 830-835
• 
  Hai Lan, Robert W. Dutton: Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs. 836-843

Panel Session - Chips of the Future: Soft, Crunchy or Hard?

• 
  Pierre G. Paulin: DATE Panel: Chips of the Future: Soft, Crunchy or Hard? 844-851

Power-Aware Networks and Interfaces

• 
  Ismail Kadayif, Mahmut T. Kandemir: Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks. 852-857
• 
  Andrea Acquaviva, Emanuele Lattanzi, Alessandro Bogliolo: Power-Aware Network Swapping for Wireless Palmtop PCs. 858-863
• 
  Nikolaos D. Liveris, Prithviraj Banerjee: Power Aware Interface Synthesis for Bus-Based SoC Design. 864-869
• 
  Alex Branover, Rakefet Kol, Ran Ginosar: Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. 870-877

Networks on Chip Design

• 
  Andrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage: An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. 878-883
• 
  Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli: ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. 884-889
• 
  Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. 890-895
• 
  Srinivasan Murali, Giovanni De Micheli: Bandwidth-Constrained Mapping of Cores onto NoC Architectures. 896-903

Advances in Technology Mapping and Circuit Sizing

• 
  Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. 904-909
• 
  Shrirang K. Karandikar, Sachin S. Sapatnekar: Fast Comparisons of Circuit Implementations. 910-915
• 
  Anurag Tiwari, Karen A. Tomko: Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs. 916-921
• 
  A. Manoj Kumar, Jayaram Bobba, V. Kamakoti: MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. 922-929

Panel Session - Nanometer Design - What are the Requirements for Manufacturing Test?

• 
  Janusz Rajski, Kan Thapar: Nanometer Design: What are the Requirements for Manufacturing Test? 930-937

Issues in Interconnect Simulation and Model Order Reduction

• 
  Joel R. Phillips, Luis Miguel Silveira: Poor Man's TBR: A Simple Model Reduction Scheme. 938-943
• 
  Peter Feldmann: Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals. 944-947
• 
  Rong Jiang, Charlie Chung-Ping Chen: SCORE: SPICE COmpatible Reluctance Extraction. 948-953
• 
  José Luis Rosselló, Jaume Segura: A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. 954-961

Emerging Technologies: From Sensors to Qubits

• 
  Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan: A Framework for Battery-Aware Sensor Management. 962-967
• 
  Phillip Stanley-Marbell, Diana Marculescu: Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance. 968-973
• 
  Pallav Gupta, Niraj K. Jha: An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. 974-979
• 
  Vivek V. Shende, Igor L. Markov, Stephen S. Bullock: Smaller Two-Qubit Circuits for Quantum Communication and Computation. 980-987

Embedded Tutorial - Architectures and Design Techniques for Energy-Efficient Embedded DSP and Multimedia Processing

• 
  Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis: Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. 988-995

Platform-Based Design and VC Reuse Methods

• 
  Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel: Measurement of IP Qualification Costs and Benefits. 996-1001
• 
  Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Architecture-Level Performance Estimation for IP-Based Embedded Systems. 1002-1007
• 
  Montek Singh, Michael Theobald: Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures. 1008-1013
• 
  M. Bolado, Hector Posadas, Javier Castillo, Pablo Huerta, Pablo Sánchez, C. Sánchez, H. Fouren, Francisco Blasco: Platform Based on Open-Source Cores for Industrial Applications. 1014-1019
• 
  Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan: MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. 1020-1027

Real-Time Issues in Embedded Systems

• 
  Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov, Magnus Hellring, Olof Bridal: Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application. 1027-1033
• 
  Yudong Tan, Vincent John Mooney III: Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches. 1034-1039
• 
  Alexander Maxiaguine, Simon Künzli, Lothar Thiele: Workload Characterization Model for Tasks with Variable Execution Demand. 1040-1045
• 
  Marek Jersak, Rafik Henia, Rolf Ernst: Context-Aware Performance Analysis for Efficient Embedded System Design. 1046-1051
• 
  Stacey Shogan, Bruce R. Childers: Compact Binaries with Code Compression in a Software Dynamic Translator. 1052-1059

Real-Life Defect Modelling and Detection

• 
  Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng: Pattern Selection for Testing of Deep Sub-Micron Timing Defects. 160
• 
  Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer: Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. 1066-1071
• 
  Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. 1072-1077
• 
  Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. 1078-1083
• 
  Zaid Al-Ars, A. J. van de Goor: Soft Faults and the Importance of Stresses in Memory Testing. 1084-1091

Optimisation in Physical Design

• 
  Chuan Lin, Hai Zhou: Wire Retiming for System-on-Chip by Fixpoint Computation. 1092-1097
• 
  Andrew B. Kahng, Igor L. Markov, Sherief Reda: Boosting: Min-Cut Placement with Improved Signal Delay. 1098-1103
• 
  Liang Deng, Martin D. F. Wong: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus. 1104-1109
• 
  Suvodeep Gupta, Srinivas Katkoori: A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk. 1110-1115
• 
  Jinjun Xiong, Lei He: Full-Chip Multilevel Routing for Power and Signal Integrity. 1116-1123

Hot Topic - Platforms and Tools for Energy-Efficient Design of Multimedia Systems

• 
  Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau: Energy-Aware System Design for Wireless Multimedia. 1124-1131

Communication Design for MPSoC

• 
  Mohamed-Anouar Dziri, Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya: Unified Component Integration Flow for Multi-Processor SoC Design and Validation. 1132-1137
• 
  Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi: An Interconnect Channel Design Methodology for High Performance Integrated Circuits. 1138-1143
• 
  Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. 1144-1149
• 
  Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee: Supporting Cache Coherence in Heterogeneous Multiprocessor Systems. 1150-1157

Combining Static and Dynamic Software Optimisation

• 
  Ismail Kadayif, Mahmut T. Kandemir, Ibrahim Kolcu: Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors. 1158-1163
• 
  Claudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli: Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications. 1164-1169
• 
  Ying Zhang, Krishnendu Chakrabarty: Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems. 1170-1175
• 
  Luis Alejandro Cortés, Petru Eles, Zebo Peng: Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks. 1176-1183

Hot Topic - The Status of the New IEEE Test Standards

• 
  Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. 1184-1191

Modelling and Estimation in Circuit Layout

• 
  Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska: Eliminating False Positives in Crosstalk Noise Analysis. 1192-1197
• 
  Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal: A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. 1198-1203
• 
  Yi-Lin Hsieh, Tsai-Ming Hsieh: A New Effective Congestion Model in Floorplan Design. 1204-1209
• 
  Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu: ULSI Interconnect Length Distribution Model Considering Core Utilization. 1210-1217

Applications of Reconfigurability

• 
  Alberto La Rosa, Claudio Passerone, Francesco Gregoretti, Luciano Lavagno: Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform. 1218-1223
• 
  Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins: Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. 1224-1229
• 
  Sami Khawam, Sajid Baloch, Arjun Pai, Imran Ahmed, Nizamettin Aydin, Tughrul Arslan, Fred Westall: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays. 1230-1235
• 
  Helena Krupnova: Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience. 1236-1243

Interconnect Modelling for MPSoC

• 
  Xinping Zhu, Sharad Malik: Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. 1244-1249
• 
  Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha: A Power and Performance Model for Network-on-Chip Architectures. 1250-1255
• 
  Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. 1256-1263

Embedded Software Generation and Optimisation

• 
  Manish Verma, Lars Wehmeyer, Peter Marwedel: Cache-Aware Scratchpad Allocation Algorithm. 1264-1269
• 
  Markus Lorenz, Peter Marwedel: Phase Coupled Code Generation for DSPs Using a Genetic Algorithm. 1270-1275
• 
  Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. 1276-1283

Scan-Based Testing

• 
  Mohammad H. Tehranipour, Mehrdad Nourani, Krishnendu Chakrabarty: Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression. 1284-1289
• 
  Baris Arslan, Alex Orailoglu: CircularScan: A Scan Architecture for Test Cost Reduction. 1290-1295
• 
  Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar: Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. 1296-1301
• 
  Andreas Leininger, Michael Gössel, Peter Muhmenthaler: Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code. 1302-1309

Novel Approaches to Analogue Simulation

• 
  Bo Wan, C.-J. Richard Shi: Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. 1310-1315
• 
  Lihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang: Direct Nonlinear Order Reduction with Variational Analysis. 1316-1321
• 
  Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. 1322-1326
• 
  Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. 1327-1333

Embedded Tutorial - System Verilog for VHDL Users

• 
  Tom Fitzpatric: System Verilog for VHDL Users. 1334-1341

Hot Topic - Quo Vadis Multimedia? From Desktop Multimedia to Distributed Multimedia Systems

• 
  Radu Marculescu, Massoud Pedram, Jörg Henkel: Distributed Multimedia System Design: A Holistic Perspective. 1342-1349

Interactive Presentations

• 
  Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout: Adaptive Prefetching for Multimedia Applications in Embedded Systems. 1350-1351
• 
  Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir: Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases. 1352-1353
• 
  George F. Viamontes, Igor L. Markov, John P. Hayes: High-Performance QuIDD-Based Simulation of Quantum Circuits. 1354-1355
• 
  D. K. Reed, Steven P. Levitan, J. Boles, Jose A. Martinez, Donald M. Chiarulli: An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation. 1356-1357
• 
  Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi: Fault Tolerance of Programmable Switch Blocks. 1358-1359
• 
  Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel: A New Self-Checking Sum-Bit Duplicated Carry-Select Adder. 1360-1361
• 
  Luis Elvira, Ferran Martorell, Xavier Aragonès, José Luis González: A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation. 1362-1363
• 
  Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri: Accurate Estimation of Parasitic Capacitances in Analog Circuits. 1364-1365
• 
  Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha: GRAAL - A Development Framework for Embedded Graphics Accelerators. 1366-1367
• 
  Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou: From Synchronous to Asynchronous: An Automatic Approach. 1368-1369
• 
  Oussama Laouamri, Chouki Aktouf: Enhancing Testability of System on Chips Using Network Management Protocols. 1370-1371
• 
  Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger: Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique. 1372-1373
• 
  Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. 1374-1375
• 
  André C. Nácul, Tony Givargis: Dynamic Voltage and Cache Reconfiguration for Low Power. 1376-1379
• 
  Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft: Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models. 1380-1381
• 
  Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software. 1382-1383
• 
  Abhinav Agrawal, Niraj K. Jha: Synthesis of Reversible Logic. 1384-1385
• 
  Matthew M. Ziegler, Mircea R. Stan: A Unified Design Space for Regular Parallel Prefix Adders. 1386-1387
• 
  Abusaleh M. Jabir, Dhiraj K. Pradhan: MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. 1388-1389
• 
  Mario R. Casu, Luca Macchiarulo: Issues in Implementing Latency Insensitive Protocols. 1390-1391
• 
  Tim Schattkowsky, Wolfgang Müller: Model-Based Specification and Execution of Embedded Real-Time Systems. 1392-1393
• 
  Satnam Singh: A Demonstration of Co-Design and Co-Verification in a Synchronous Language. 1394-1395
• 
  Shukang Zhou, Bruce R. Childers, Naveen Kumar: Profile Guided Management of Code Partitions for Embedded Systems. 1396-1399
• 
  Rong Jiang, Charlie Chung-Ping Chen: Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. 1400-1401
• 
  Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten: Statistically Aware Buffer Planning. 1402-1403
• 
  S. Bernardini, Jean Michel Portal, Pascal Masson: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. 1404-1405
• 
  Josep Rius Vázquez, José Pineda de Gyvez: Power Supply Noise Monitor for Signal Integrity Faults. 1406-1407
• 
  Mehdi Baradaran Tahoori, Fabrizio Lombardi: Testing of Quantum Dot Cellular Automata Based Designs. 1408-1409
• 
  Jacob R. Minz, Mohit Pathak, Sung Kyu Lim: Net and Pin Distribution for 3D Package Global Routing. 1410-1411
• 
  Markus Olbrich, Erich Barke: Placement Using a Localization Probability Model (LPM). 1412
• 
  Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost: CMOS Structures Suitable for Secured Hardware. 1414-1415
• 
  Kambiz Rahimi, Seth Bridges, Chris Diorio: Timing Correction and Optimization with Adaptive Delay Sequential Element. 1416

last updated on Sat May 18 04:50:12 2013 by the dblp team
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