Plenary - Keynote Session

• 
  Hugo De Man: On Nanoscale Integration and Gigascale Complexity in the Post.Com World. 12
• 
  Taylor Scanlon: Global Responsibilities in SOC Design. 12

How to Choose Semiconductor IP?

• 
  Ian Phillips: How to Choose Semiconductor IP? - Embedded Processor. 14
• 
  Vincent Ratford: Make Your SoC Design a Winner: Select the Right Memory IP. 15
• 
  Grant Martin: How to Choose Semiconductor IP: Embedded Software. 16
• 
  Pierre Bricaud: IP Day: How to Choose Semiconductor IP? 17

Formal Verification of Complex Designs

• 
  Roope Kaivola, Naren Narasimhan: Formal Verification of the Pentium ® 4 Floating-Point Multiplier. 20-27
• 
  Miroslav N. Velev: Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer. 28-35
• 
  Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. 36-43
• 
  Marco A. Peña, Jordi Cortadella, Alexander B. Smirnov, Enric Pastor: A Case Study for the Verification of Complex Timed Circuits: IPCMOS. 44-51

Cooling Layout Arrangements

• 
  Juan de Vicente, Juan Lanchares, Román Hermida: FPGA Placement by Thermodynamic Combinatorial Optimization. 54-60
• 
  Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin: An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. 61-68
• 
  Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang: Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. 69-75

Defect Oriented Test

• 
  Michael Pronath, Helmut E. Graeb, Kurt Antreich: A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. 78-83
• 
  Saravanan Padmanaban, Spyros Tragoudas: Exact Grading of Multiple Path Delay Faults. 84-88
• 
  Zaid Al-Ars, A. J. van de Goor: Modeling Techniques and Tests for Partial Faults in Memory Devices. 89-93
• 
  Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer: A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. 94-99

Power Analysis and Management in Networks and Processors

• 
  Davide Bertozzi, Luca Benini, Giovanni De Micheli: Low Power Error Resilient Encoding for On-Chip Data Buses. 102-109
• 
  Tajana Simunic, Stephen P. Boyd: Managing Power Consumption in Networks on Chip. 110-116
• 
  Sandy Irani, Rajesh K. Gupta, Sandeep K. Shukla: Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States. 117-123
• 
  Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose: AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. 124-129

Panel - What is the Right IP Business Model?

• 
  Vernon P. Essi Jr.: IP is All About Implementation and Customer Satisfaction. 132

SAT and BDD Techniques

• 
  Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton: Using Problem Symmetry in Search Based Satisfiability Algorithms. 134-141
• 
  Evguenii I. Goldberg, Yakov Novikov: BerkMin: A Fast and Robust Sat-Solver. 142-149
• 
  Gianpiero Cabodi, Paolo Camurati, Stefano Quer: Dynamic Scheduling and Clustering in Symbolic Image Computation. 150-156

Technology and Interconnect Issues in Low Power Design

• 
  Luca Macchiarulo, Enrico Macii, Massimo Poncino: Wire Placement for Crosstalk Energy Minimization in Address Buses. 158-162
• 
  Chris H. Kim, Kaushik Roy: Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. 163-167
• 
  Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau: Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. 168-175
• 
  Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska: Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. 176-183

Advanced Mixed Signal Test

• 
  Ramakrishna Voorakaranam, Sasikumar Cherubal, Abhijit Chatterjee: A Signature Test Framework for Rapid Production Testing of RF Circuits. 186-191
• 
  Carlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu: Analog IP Testing: Diagnosis and Optimization. 192-196
• 
  Christoph Hoffmann: A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits. 197-204
• 
  Yolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho: Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics. 205-211

Collaborative Design

• 
  L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier: E-Design Based on the Reuse Paradigm. 214-220
• 
  André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová: Internet-Based Collaborative Test Generation with MOSCITO. 221-226
• 
  Tom J. Kazmierski, Neil Clayton: A Two-Tier Distributed Electronic Design Framework. 227-231
• 
  Achim Rettberg, Wolfgang Thronicke: Embedded System Design Based On Webservices. 232-236

Panel - Who Owns the Platform?

• 
  Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier: Who Owns the Platform? 238

Embedded Tutorial - The Need for Infrastructure IP in SoCs

• 
  Michael Nicolaidis: IP for Embedded Robustness. 240-241
• 
  Stephen Pateras: Embedded Diagnosis IP. 242-243
• 
  Eric Dupont, Michael Nicolaidis, Peter Rohr: Embedded Robustness Ips. 244-245

Advances in Logic Synthesis

• 
  Sezer Gören, F. Joel Ferguson: CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. 248-254
• 
  Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver: Generalized Early Evaluation in Self-Timed Circuits. 255-259
• 
  Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang: Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. 260-265

Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design

• 
  Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen: A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics. 268-273
• 
  Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke: Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. 274-278
• 
  Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen: Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices. 279-284
• 
  Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. 285-289

EDA Tools for RF: Myth or Reality?

• 
  EDA Tools for RF: Myth or Reality? 292-293

Platform-Based Design and Virtual-Component Reuse

• 
  Tin-Man Lee, Wayne Wolf, Jörg Henkel: Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs. 296-301
• 
  Robert Pasko, Serge Vernalde, Patrick Schaumont: Techniques to Evolve a C++ Based System Design Language. 302-309
• 
  Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid: A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. 310-314

Analogue Circuit Characterisation and Simulation

• 
  W. Rahajandraibe, Christian Dufaza, Daniel Auvergne, B. Cialdella, B. Majoux, V. Chowdhury: Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. 316-321
• 
  S. Lampe, S. Laur: Global Optimization Applied to the Oscillator Problem. 322-326

Panel - MEDEA+ and ITRS Roadmaps

• 
  Joseph Borel, G. Matheron, Ahmed Amine Jerraya, S. Resve, M. Rogers, Wolfgang Rosenstiel, Irmtraud Rugen-Herzig, F. Theewen: MEDEA+ and ITRS Roadmaps. 328

Asynchronous Circuits and Clock Scheduling

• 
  Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards: A Burst-Mode Oriented Back-End for the Balsa Synthesis System. 330-337
• 
  Victor Khomenko, Maciej Koutny, Alexandre Yakovlev: Detecting State Coding Conflicts in STGs Using Integer Programming. 338-345
• 
  Soha Hassoun, Eduardo Calvillo-Gámez, Christopher Cromer: Verifying Clock Schedules in the Presence of Cross Talk. 346-350

Analogue and Mixed-Signal Systems

• 
  Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay: Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . 352-356
• 
  Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen: Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter. 357-361
• 
  Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez: Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip. 362-366

BIST Diagnosis and DFT

• 
  Amit R. Pandey, Janak H. Patel: An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. 368-375
• 
  Ismet Bayraktaroglu, Alex Orailoglu: Gate Level Fault Diagnosis in Scan-Based BIST. 376-381
• 
  Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel: An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment. 382-386
• 
  Sherief Reda, Alex Orailoglu: Reducing Test Application Time Through Test Data Mutation Encoding. 387-393

Code and Memory Optimization in Co-Design

• 
  Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch: Hardware/Software Trade-Offs for Advanced 3G Channel Coding. 396-401
• 
  Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau: An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. 402-408
• 
  Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter Marwedel: Assigning Program and Data Objects to Scratchpad for Energy Reduction. 409-415

Network on a Chip

• 
  Giovanni De Micheli, Luca Benini: Networks on Chip: A New Paradigm for Systems on Chip Design. 418-419
• 
  Joseph Williams, Nevin Heintze, Bryan D. Ackland: Communication Mechanisms for Parallel DSP Systems on a Chip. 420-422
• 
  Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen: Networks on Silicon: Combining Best-Effort and Guaranteed Services. 423-425

Low Power Architectures and Software

• 
  Tanja Van Achteren, Geert Deconinck, Francky Catthoor, Rudy Lauwereins: Data Reuse Exploration Techniques for Loop-Dominated Application. 428-435
• 
  Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam: EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. 436-442
• 
  Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau: Power Savings in Embedded Processors through Decode Filer Cache. 443-448
• 
  Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii: Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. 449-453

Nitty Gritty Details of Layout Design

• 
  Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . 456-463
• 
  Goeran Jerke, Jens Lienig: Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits. 464-469
• 
  Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu: A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. 470-475

SoC and System Test

• 
  Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu: Test Planning and Design Space Exploration in a Core-Based Environment. 478-485
• 
  Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin: A Hierarchical Test Scheme for System-On-Chip Designs. 486-490
• 
  Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient Wrapper/TAM Co-Optimization for Large SOCs. 491-498
• 
  Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei: Beyond UML to an End-of-Line Functional Test Engine. 499-503

Modelling and Synthesis of Embedded Systems

• 
  Kai Richter, Rolf Ernst: Event Model Interfaces for Heterogeneous System Analysis. 506-513
• 
  Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles: Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems. 514-521
• 
  JoAnn M. Paul, Donald E. Thomas: A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. 522-528
• 
  Daniel Menard, Olivier Sentieys: Automatic Evaluation of the Accuracy of Fixed-Point Algorithms. 529-535

Panel - Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs

• 
  K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment: Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. 538

Reconfigurable Architectures

• 
  Davide Rizzo, Osvaldo Colavin: A Video Compression Case Study on a Reconfigurable VLIW Architecture. 540-546
• 
  Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi: A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. 547-552
• 
  Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy: Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. 553-558
• 
  Jürgen Teich, Markus Köster: (Self-)reconfigurable Finite State Machines: Theory and Implementation. 559-566

Analogue Modelling, Layout and Sizing

• 
  Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi: A Linear-Centric Simulation Framework for Parametric Fluctuations. 568-575
• 
  Mohamed Dessouky, DiaaEldin Sayed: Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio. 576-580
• 
  Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb: Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. 581-585
• 
  Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst: High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. 586-590

Test Resource Partitioning for Embedded Cores

• 
  Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Effective Software Self-Test Methodology for Processor Cores. 592-597
• 
  Anshuman Chandra, Krishnendu Chakrabarty: Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression. 598-603
• 
  Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. 604-611
• 
  Michele Favalli, Cecilia Metra: Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. 612-617

System Level Simulation and Modelling

• 
  Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya: Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design. 620-627
• 
  Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter: Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. 628-633
• 
  Peng Li, Lawrence T. Pileggi: A Linear-Centric Modeling Approach to Harmonic Balance Analysis. 634-639
• 
  Paul I. Pénzes, Alain J. Martin: An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor. 640-647

Deep Submicron Design and Timing Closure

• 
  Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld: Design Automation for Deepsubmicron: Present and Future. 650-657

Reconfigurable SoC - What Will it Look Like?

• 
  J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan: Reconfigurable SoC - What Will it Look Like? 660-662

Layout Aware Logic Synthesis

• 
  Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Congestion-Aware Logic Synthesis. 664-671
• 
  Thomas Kutzschebauch, Leon Stok: Layout Driven Decomposition with Congestion Consideration. 672-676
• 
  Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas P. P. P. van Ginneken: Improving Placement under the Constant Delay Model. 677-682
• 
  Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang: Crosstalk Alleviation for Dynamic PLAs. 683-687

Buffering and Tapering

• 
  Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao: Flip-Flop and Repeater Insertion for Early Interconnect Planning. 690-695
• 
  Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young: Congestion Estimation with Buffer Planning in Floorplan Design. 696-701
• 
  Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao: Maze Routing with Buffer Insertion under Transition Time Constraints. 702-707
• 
  Li Ding, Pinaki Mazumder: Optimal Transistor Tapering for High-Speed CMOS Circuits. 708-713

Automatic Design Debug and TPG

• 
  Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir: Incremental Diagnosis and Correction of Multiple Faults and Errors. 716-721
• 
  Irith Pomeranz, Sudhakar M. Reddy: Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. 722-729
• 
  Vivekananda M. Vedula, Jacob A. Abraham: FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. 730-734

Object Oriented System Specification and Design

• 
  Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta, Masato Otsuka: An Environment for Dynamic Component Composition for Efficient Co-Design . 736-743
• 
  Fabrizio Ferrandi, Michele Rendine, Donatella Sciuto: Functional Verification for SystemC Descriptions Using Constraint Solving. 744-751
• 
  M. D. Edwards, P. N. Green: The Modelling of Embedded Systems Using HASoC. 752-759
• 
  Alex Doboli, Ranga Vemuri: A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. 760-767

UML: Using the Unified Modeling Language for Embedded System Specification

• 
  Bran Selic: The Real-Time UML Standard: Definition and Application. 770-772
• 
  Grant Martin: UML for Embedded Systems Specification and Design: Motivation and Overview. 773-775
• 
  Gjalt G. de Jong: A UML-Based Design Methodology for Real-Time and Embedded Sytems. 776-779

Real-Time Embedded Systems

• 
  Gang Quan, Xiaobo Hu: Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor. 782-787
• 
  Woonseok Kim, Jihong Kim, Sang Lyul Min: A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis. 788-794
• 
  George Logothetis, Klaus Schneider: Extending Synchronous Languages for Generating Abstract Real-Time Models. 795-802

Interconnect Modelling

• 
  David Goren, Michael Zelikson, Tiberiu C. Galambos, Rachel Gordin, Betty Livshitz, Alon Amir, Anatoly Sherman, Israel A. Wagner: An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach . 804-811
• 
  Lauren Hui Chen, Malgorzata Marek-Sadowska: Closed-Form Crosstalk Noise Metrics for Physical Design Applications. 812-819
• 
  Qinwei Xu, Pinaki Mazumder: Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects. 820-825
• 
  Bernard N. Sheehan: Library Compatible Ceff for Gate-Level Timing. 826-830

On-Line Testing and Fault Tolerance

• 
  Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli: Self-Checking Scheme for the On-Line Testing of Power Supply Noise. 832-836
• 
  Régis Leveugle: Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. 837-841
• 
  Kaijie Wu, Ramesh Karri: Exploiting Idle Cycles for Algorithm Level Re-Computing. 842-846
• 
  Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López: New Techniques for Speeding-Up Fault-Injection Campaigns. 847-852

Design Space Evaluation

• 
  Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst: System Design for Flexibility. 854-861
• 
  Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee: Accurate Area and Delay Estimators for FPGAs. 862-869
• 
  Klaus Buchenrieder, Andreas Pyttel, Alexander Sedlmeier: A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering. 870-874
• 
  Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta: Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation. 875-881

From System Specification to Layout: Seamless Top-Down Design Methods for Analogue and Mixed Signal Applications

• 
  Ralf Sommer, Irmtraud Rugen-Herzig, Eckhard Hennig, Umberto Gatti, Piero Malcovati, Franco Maloberti, Karsten Einwich, Christoph Clauß, Peter Schwarz, G. Noessing: From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications. 884-891

Architectural Level Synthesis

• 
  Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Memory System Connectivity Exploration. 894-901
• 
  Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke: Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. 902-908
• 
  María C. Molina, José M. Mendías, Román Hermida: Multiple-Precision Circuits Allocation Independent of Data-Objects Length. 909-913

Advanced Linear Modelling Techniques

• 
  Emad Gad, Michel S. Nakhla: Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function. 916-922
• 
  Carlos P. Coelho, Luis Miguel Silveira, Joel R. Phillips: Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation. 923-930
• 
  Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. 931-935

Memory Testing and ATPG Issues

• 
  Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: An Optimal Algorithm for the Automatic Generation of March Tests. 938-943
• 
  A. J. van de Goor, Magdy S. Abadir, Alan Carlin: Minimal Test for Coupling Faults in Word-Oriented Memories. 944-948
• 
  Michael S. Hsiao: Maximizing Impossibilities for Untestable Fault Identification. 949-953
• 
  Soumitra Bose: Automated Modeling of Custom Digital Circuits for Test. 954-961

Embedded Software Performance Analysis and Optimization

• 
  G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe: False Path Elimination in Quasi-Static Scheduling. 964-970
• 
  Gianluca Bontempi, Wido Kruijtzer: A Data Analysis Method for Software Performance Prediction. 971-976
• 
  Nikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios Soudris, Constantinos E. Goutis: A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. 977-983
• 
  Mahmut T. Kandemir: A Compiler-Based Approach for Improving Intra-Iteration Data Reuse. 984-990

Technical Plenary - 40 Years of EDA

• 
  Joseph Borel: European CAD from the 60's to the New Millenium. 992

Design Technology for Networked Reconfigurable FPGA Platforms

• 
  Steve Guccione, Diederik Verkest, Ivo Bolsens: Design Technology for Networked Reconfigurable FPGA Platforms. 994-997

High-Level Synthesis and Asynchronous Pipelines

• 
  Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick: High-Speed Non-Linear Asynchronous Pipelines. 1000-1007
• 
  Marcos Ferretti, Peter A. Beerel: Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding. 1008-1015
• 
  Chunhong Chen, Majid Sarrafzadeh: Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. 1016-1020
• 
  Qin Zhao, Bart Mesman, Twan Basten: Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models. 1021-1026

Coupling and Switching Noise Modelling within Integrated Circuits

• 
  Thomas Brandtner, Robert Weigel: Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network. 1028-1032
• 
  B. L. A. Van Thielen, G. A. E. Vandenbosch: Fast Method to Include Parasitic Coupling in Circuit Simulations. 1033-1037
• 
  Li Ding, Pinaki Mazumder: Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling. 1038-1043
• 
  Igor S. Stievano, Flavio G. Canavero, Ivan A. Maio, Z. Chen, Wiren D. Becker, George A. Katopis: Macromodeling of Digital I/O Ports for System EMC Assessment . 1044-1048

Formal Verification Techniques: Industrial Status and Perspectives

• 
  Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud: Formal Verification Techniques: Industrial Status and Perspectives. 1050

Power Optimization for Embedded Processor

• 
  Armita Peymandoust, Tajana Simunic, Giovanni De Micheli: Low Power Embedded Software Optimization Using Symbolic Algebra. 1052-1058
• 
  Tiehan Lv, Wayne Wolf, Jörg Henkel, Haris Lekatsas: An Adaptive Dictionary Encoding Scheme for SOC Data Buses. 1059-1064
• 
  Peter Petrov, Alex Orailoglu: Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches. 1065-1071
• 
  Martin Palkovic, Miguel Miranda, Francky Catthoor: Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities. 1072-1077

Poster Sessions

• 
  Walter Hartong, Lars Hedrich, Erich Barke: An Approach to Model Checking for Nonlinear Analog Systems. 1080
• 
  Slawomir Pilarski, Gracia Hu: Speeding up SAT for EDA. 1081
• 
  Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah: Search-Based SAT Using Zero-Suppressed BDDs. 1082
• 
  Manuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst: An Encoding Technique for Low Power CMOS Implementations of Controllers. 1083
• 
  Elena Dubrova: Composition Trees in Finding Best Variable Orderings for ROBDDs. 1084
• 
  Joerg Abke, Erich Barke: A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . 1085
• 
  Peyman Rezvani, Massoud Pedram: Concurrent and Selective Logic Extraction with Timing Consideration. 1086
• 
  Dariusz Kania: Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions. 1087
• 
  Michel R. C. M. Berkelaar, Koen van Eijk: Efficient and Effective Redundancy Removal for Million-Gate Circuits. 1088
• 
  Alexandre V. Bystrov, Maciej Koutny, Alexandre Yakovlev: Visualization of Partial Order Models in VLSI Design Flow. 1089
• 
  Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. 1090
• 
  Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Power-Efficient Trace Caches. 1091
• 
  Mahmut T. Kandemir, Ibrahim Kolcu: Reducing Cache Access Energy in Array-Intensive Application. 1092
• 
  Carsten Nitsch, Udo Kebschull: The Use of Runtime Configuration Capabilities for Networked Embedded Systems. 1093
• 
  Iouliia Skliarova, António de Brito Ferrari: A SAT Solver Using Software and Reconfigurable Hardware. 1094
• 
  Ralf Münzenberger, Matthias Dörfel, Frank Slomka, Richard Hofmann: A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems. 1095
• 
  Martin Grajcar, Werner Grass: Improved Constraints for Multiprocessor System Scheduling. 1096
• 
  Olga Peñalba, José M. Mendías, Román Hermida: Maximizing Conditonal Reuse by Pre-Synthesis Transformations. 1097
• 
  Sunan Tugsinavisut, Peter A. Beerel: Control Circuit Templates for Asynchronous Bundled-Data Pipelines. 1098
• 
  Olivier Peyran, Wenjun Zhuang: Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures. 1099
• 
  Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh: A New Formulation for SOC Floorplan Area Minimization Problem. 1100
• 
  Chris C. N. Chu, Evangeline F. Y. Young: Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. 1101
• 
  Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah: EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses. 1102
• 
  Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner: Estimation of Power Consumption in Encoded Data Buses. 1103
• 
  Tran chi Hieu: Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis. 1104
• 
  Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli: Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques. 1105
• 
  Mircea R. Stan, Avishek Panigrahi: The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits. 1106
• 
  Andreia Cathelin, D. Saias, Didier Belot, Y. Leclercq, F. Clément: Substrate Parasitic Extraction for RF Integrated Circuits. 1107
• 
  David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: A Complete Phase-Locked Loop Power Consumption Model. 1108
• 
  Cristinel Ababei, Kia Bazargan: Statistical Timing Driven Partitioning for VLSI Circuits. 1109
• 
  Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen: DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. 1110
• 
  A. Hassibi, Maria del Mar Hershenson: Automated Optimal Design of Switched-Capacitor Filters. 1111
• 
  Tao Lin, Michael W. Beattie, Lawrence T. Pileggi: On-Chip Inductance Models: 3D or Not 3D? 1112
• 
  Hasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe: Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate. 1113
• 
  Roni Khazaka, Michel S. Nakhla: Compact Macromodel for Lossy Coupled Transmission Lines. 1114
• 
  Jean-Luc Levant, Mohammed Ramdani: An EMC-Compliant Design Method of High-Density Integrated Circuits. 1115
• 
  Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy: Finding a Common Fault Response for Diagnosis during Silicon Debug. 1116
• 
  Suriya Ashok Kumar, Rafic Z. Makki, David M. Binkley: I_DDT Testing of Embedded CMOS SRAMs. 1117
• 
  Swarup Bhunia, Kaushik Roy: Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. 1118
• 
  Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen: An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. 1119
• 
  Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet: On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems. 1120
• 
  Rohit Kapur, Thomas W. Williams, M. Ray Mercer: Directed-Binary Search in Logic BIST Diagnostics. 1121
• 
  Michele Favalli, Marcello Dalpasso: An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators. 1122
• 
  Irith Pomeranz, Yervant Zorian: Fault Isolation Using Tests for Non-Isolated Blocks. 1123
• 
  Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: A Heuristic for Test Scheduling at System Level. 1124
• 
  Sandeep Koranne, Vishal Suhas Choudhary: Formulation of SOC Test Scheduling as a Network Transportation Problem. 1125
• 
  Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira: A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs. 1126
• 
  Alexander V. Drozd, M. V. Lobachev, J. V. Drozd: Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider. 1127
• 
  Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon: An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores. 1128
• 
  Anton Sauer, Günter Elst, Ludger Krahn, Werner John: The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines. 1129
• 
  Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis: Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments. 1130
• 
  Bernd Stöhr, Michael Simmons, Joachim Geishauser: FlexBench: Reuse of Verification IP to Increase Productivity. 1131
• 
  Juha-Pekka Soininen, Jari Kreku, Yang Qu: Mappability Estimation of Architecture and Algorithm. 1132
• 
  Peter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç: Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS. 1133
• 
  Klaus Hering: A Parallel LCC Simulation System. 1134
• 
  Francesco Bruschi, Michele Chiamenti, Fabrizio Ferrandi, Donatella Sciuto: Error Simulation Based on the SystemC Design Description Language. 1135
• 
  Dag Björklund, Johan Lilius: Towards a Kernel Language for Heterogeneous Computing. 1136
• 
  Lukai Cai, Daniel Gajski, Paul Kritzinger, Mike Olivarez: Top-Down System Level Design Methodology Using SpecC, VCC and SystemC. 1137
• 
  Laura Pozzi, Miljan Vuletic, Paolo Ienne: Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. 1138
• 
  Hans Georg Brachtendorf, S. Lampe, Rainer Laur, Robert C. Melville, Peter Feldmann: Steady State Calculation of Oscillators Using Continuation Methods. 1139

last updated on Sat May 18 04:50:13 2013 by the dblp team
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