DASIP 2011: Tampere, Finland
Jari Nurmi, Tapani Ahonen (Eds.):
2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, November 2-4, 2011.
IEEE 2011, ISBN 978-1-4577-0620-2 
System simulation and processor generation
- Julien Peeters, Nicolas Ventroux, Tanguy Sassolas, Lionel Lacassagne:
A systemc TLM framework for distributed simulation of complex systems with unpredictable communication.
12-19
- Takieddine Majdoub, Sébastien LeNours, Olivier Pasquier, Fabienne Nouvel:
Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach.
20-26
- Mathieu Rosiere, Jean Lou Desbarbieux, Nathalie Drach, Franck Wajsbürt:
Morpheo: A high-performance processor generator for a FPGA implementation.
27-34
- Nicolas Siret, Jean-François Nezan, Aimad Rhatay:
Design of a processor optimized for syntax parsing in video decoders.
35-43
Low power design & methodologies
Reconfigurable systems & tools for signal & image processing - Part 1
- Vincent Brost, Charles Meunier, Debyo Saptono, Fan Yang:
Flexible VLIW processor based on FPGA for real-time image processing.
59-66
- Matthias Birk, Alexander Guth, Michael Zapf, Matthias Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker:
Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing.
67-74
- Samuel Garcia, Bertrand Granado:
Task model and online operating system API for hardware tasks in OLLAF platform.
75-81
Signal and image processing on GPU
Dynamic architectures & adaptive management for image & signal processing
Signal processing and processor designs
- A. D. Darji, Rajul Bansal, S. N. Merchant, A. N. Chandorkar:
High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform.
123-128
- Teemu Laukkarinen, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen:
Pilot studies of wireless sensor networks: Practical experiences.
129-136
- Chenglong Xiao, Emmanuel Casseau:
Efficient maximal convex custom instruction enumeration for extensible processors.
137-143
- Roberto Airoldi, Fabio Garzia, Jari Nurmi:
Efficient FFT pruning algorithm for non-contiguous OFDM systems.
144-149
- Matthieu Texier, Erwan Piriou, Mathieu Thevenin, Raphaël David:
Designing processors using MAsS, a modular and lightweight instruction-level exploration tool.
150-155
Smart image sensors
Methods & tools for dataflow programming
- Ghislain Roquier, Endri Bezati, Richard Thavot, Marco Mattavelli:
Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms.
171-177
- Francesca Palumbo, Nicola Carta, Luigi Raffo:
The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer.
178-185
- Endri Bezati, Hervé Yviquel, Mickaël Raulet, Marco Mattavelli:
A unified hardware/software co-synthesis solution for signal processing systems.
186-191
- Ab Al-Hadi Ab Rahman, Hossam Amer, Anatoly Prihozhy, Christophe Lucarz, Marco Mattavelli:
Optimization methodologies for complex FPGA-based signal processing systems with CAL.
192-199
Reconfigurable systems & tools for signal & image processing - Part 1
- Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker:
Development of a method for image-based motion estimation of a VTOL-MAV on FPGA.
201-208
- Tomasz Kryjak, Mateusz Komorkiewicz, Marek Gorgon:
Real-time moving object detection for video surveillance system in FPGA.
209-216
- Walter Stechele, Jan Hartmann, Erik Maehle:
An approach to self-learning multicore reconfiguration management applied on Robotic Vision.
217-222
- Frederic Amiel, Thomas Ea, Vashishtha Vinay:
Power consumption improvement with residue code for fault tolerance on SRAM FPGA.
223-228
Poster Session:
Main Track
- Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar:
Embedded systems security: An evaluation methodology against Side Channel Attacks.
230-237
- Andreas Dahlin, Fareed Jokhio, Johan Lilius, Jérôme Gorin, Mickaël Raulet:
Interfacing and scheduling legacy code within the Canals framework.
238-245
- Ville Kaseva, Timo D. Hämäläinen, Marko Hännikäinen:
Range-free algorithm for energy-efficient indoor localization in Wireless Sensor Networks.
246-253
- Jukka Saastamoinen, Jari Kreku:
Application workload model generation methodologies for system-level design exploration.
254-260
- Carlo Condo, Guido Masera:
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods.
261-268
- Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser:
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology.
269-276
- Mohsen Amiri Farahani, Eduardo Castillo Guerra, Bruce G. Colpitts:
A new algorithm for realization of FIR filters using multiple constant multiplications.
277-283
- Daniela Genius, Nicolas Pouillon:
Analyzing software inter-task communication channels on a clustered shared memory multi processor system-on-chip.
284-291
- Thomas Schlechter:
Multiplier free filter bank based concept for blocker detection in LTE systems.
292-298
- Markku Hänninen, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen:
Practical monitoring and analysis tool for WSN testing.
299-306
Poster Session:
Reconfigurable Systems & Tools for Signal & Image Processing
Poster Session:
Dynamic Architectures & Adaptive Management for Image & Signal Processing
Poster Session:
Smart Image Sensors
Poster Session:
Signal and Image Processing on GPU
Last update Thu May 24 04:15:58 2012
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