Dagstuhl Seminar Proceedings: Dynamically Reconfigurable Architectures 2006
Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich (Eds.): Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006 Dagstuhl Seminar Proceedings 06141- Norbert Wehn, Timo Vogt, Christian Neeb: A Reconfigurable Outer Modem Platform for Future Communications Systems.
- Peter Zipf, Manfred Glesner: Towards an Automated Design of Application-specific Reconfigurable Logic.
- Peter M. Athanas: The (empty?) Promise of FPGA Supercomputing.
- Rainer Buchty: Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution.
- Florian Dittmann: Reconfiguration Time Aware Processing on FPGAs.
- Diana Göhringer, Mateusz Majer, Jürgen Teich: Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine.
- Sven Heithecker, Amilcar do Carmo Lucas, Rolf Ernst: FlexFilm - an Image Processor for Digital Film Processing.
- Jürgen Becker, Michael Hübner, Katarina Paulsson: Physical 2D Morphware and Power Reduction Methods for Everyone.
- David A. Kearney, Mark Jasiunas: Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration.
- Douglas L. Maskell, Timothy F. Oliver: Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System.
- Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, Paul M. Heysters: Efficient architectures for streaming applications.
- Walter Stechele: Dynamically Reconfigurable Systems-on-Chip.
- Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Markus Damm, Dennis Hauser: Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs).
- József Vásárhelyi, Péter Serfözö: Analysis of Mojette Transform Implementation on Reconfigurable Hardware.
- Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, Thomas Wild: Reconfigurable Processing Units vs. Reconfigurable Interconnects.
- Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Executive Summary -- Dynamically Reconfigurable Architectures.
- Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.
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last updated on 2013-10-17T202759 by the dblp team