33. DAC 1996: Las Vegas, Nevada, USA

Executive Forum, Panel: The EDA Year in Review: CEO's, The Press, and Users

High Speed Interconnect

Panel: PCB Synthesis - Is the Technology Ready for High Speed Design?

Power Analysis

Current Directions in High Level Synthesis

Analysis and Synthesis of Asynchronous Circuits

New Frontiers in Partitioning

Trends in Verification

Panel: Hot New Trends in Verification

Specialized Design Techniques for Speed and Power

Test and Fault Tolerance in High Level Synthesis

Issues in Discrete Simulation

Issues in Design Environments

Panel: Gearing Up for the Technology Explosion

Tutorial: The SPICE FET Models: Pitfalls and Prospects

Combinational Logic Synthesis I

Pattern Generation for Test and Diagnosis

CAD for Analog and Mixed Signal ICs

Panel: Core-Based Design for System-Level ASICs - Whose Job Is It?

Panel: A Common Standards Roadmap

Combinational Logic Synthesis II

Design for Testability

Advances in Electrical Simulation

Mixed Signal Design

Panel: Mixed Signal Designs: Are There Solutions Today?

Functional Verification of Microprocessors

High Level Power Optimization

3-D Parasitic Extraction

Routing Optimization for Performance

Tutorial: How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together

Functional Verification Techniques

Power Estimation

Optimization of Sequential Circuits

Topics in Physical Design

Consumer Product Design

Tutorial: Issues and Answers in CAD Tool Interoperability

Hardware-Software Co-Design

Timing and Power

Verification of Sequential Systems

Panel: Electronic Connectivity + EDA Data = Electronic Commerce

Experience with High Level Synthesis

Analysis and Compilation for Embedded Software

Timing Modeling and Optimization

Decision Diagrams and Their Application

Formal Methods

Applications for Hardware/Software Codesign

Power Estimation and Retiming

Technology Dependent Performance Driven Synthesis

Layout Analysis and Optimization