31. DAC 1994:
San Diego, California, USA Michael J. Lorenzetti (Ed.):
Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994.
ACM Press 1994, ISBN 0-7803-1836-6 Software & Instruction Set Synthesis
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Transition Densities for Sequential Systems
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CAD for Analog and High-Performance Digital Circuits
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Management of Electronic Design Automation
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Panel
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conf/dac/CostelloRGHFCC94
Asynchronous Synthesis
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conf/dac/KondratyevKLVY94 export record as
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Ruchir Puri ,
Jun Gu :
A Modular Partitioning Approach for Asynchronous Circuit Synthesis.
63-69
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New Developments in Design for Test
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Pranav Ashar ,
Sharad Malik :
Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications.
77-80
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Timing Analysis
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Managing The Design Process
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Sean Murphy :
Partnering with EDA Vendors: Tips, Techniques, and the Role of Standards.
131-134
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Wojciech Maly :
Cost of Silicon Viewed from VLSI Design Perspective.
135-142
Estimation & Synthesis of Memory Structures
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Intellectual Property
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Panel
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conf/dac/CleemputDBCHLF94
Technology-Driven Routing
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Kai Zhu ,
D. F. Wong :
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs.
165-170
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conf/dac/MadhwapathySBP94
Panel
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data-Path Synthesis & Test
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conf/dac/BhattacharyaDB94 export record as
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Topics in Verification and Diagnosis
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FPGA Partitioning and Optimization
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Design Implementation
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BDD Techniques and Formal Verification
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Panel
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conf/dac/AbrahamKPdDLSW94
FPGA Placement & Routing
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Formal Verification
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Panel
Layout and Technology Dependent Synthesis
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Delay and Self Test
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Routing for High Performance
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Panel
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Logic Synthesis
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Shin-ichi Minato :
Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs.
420-424
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Tutorial:
Hardware-Software Co-Design
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Design Representations and Data Structures for High Level Design
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Design Methodology
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Scheduling
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conf/dac/BhattacharyaDB94a
CAD Algorithms in Non-CAD Problems
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Fault Simulation and Diagnosis
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World Class Electronic Design Methodologies I
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Kenneth A. Radtke :
The AT&T 5ESS Hardware Design Environment: A Large System's Hardware design Process.
527-531
New Ideas in High-level Synthesis
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Panel
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Electrical and Thermal Analysis
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Chung-Jung Chen ,
Wu-Shiung Feng :
Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation.
581-585
World Class Design Methodologies II
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Thomas F. Fox :
The Design of High-Performance Microprocessors at Digital.
586-591
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Formal Verification of Systems
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Interconnect Analysis
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Tuyen V. Nguyen :
Efficient Simulation of Lossy and Dispersive Transmission Lines.
622-627
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Circuit Partitioning
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Panel
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Sequential Synthesis
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conf/dac/KrishnamoorthyM94
New Techniques in Test Generation
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Discrete Simulation
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Bhanu Kapoor :
Improving the Accuracy of Circuit Activity Measurement.
734-739
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