24. DAC 1987:
Miami Beach, Florida, USA A. O'Neill , D. Thomas (Eds.):
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, June 28 - July 1, 1987.
IEEE Computer Society Press / ACM 1987
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M. C. Chi :
An Automatic Rectilinear Partitioning Procedure for Standard Cells.
50-55
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Lov K. Grover :
Standard Cell Placement Using Simulated Sintering.
56-59
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V. Masurkar :
Requirements for a Practical Software Engineering Environment.
67-73
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N. J. Elias :
A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator.
82-88
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conf/dac/VladimirescuWKBKDNJL87 export record as
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M. T. Smith :
A Hardware Switch Level Simulator for Large MOS Circuits.
95-100
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Kye S. Hedlund :
Aesop: A Tool for Automated Transistor Sizing.
114-120
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D. B. Polkl :
A Three-Layer Gridless Channel Router with Compaction.
146-151
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H. H. Chen :
Routing L-Shaped Channels in Nonslicing-Structure Placement.
152-158
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Wojciech Maly :
Realistic Fault Modeling for VLSI Testing.
173-180
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S. Chowdhury :
An Automated Design of Minimum-Area IC Power/Ground Nets.
223-229
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Daniel Weise :
Functional Verification of MOS Circuits.
265-270
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conf/dac/ChandrasekharPC87 export record as
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Bryan Preas :
Benchmarks for Cell-Based Layout Systems.
319-320
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Kurt Keutzer :
DAGON: Technology Binding and Local Optimization by DAG Matching.
341-347
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J. Apte ,
Gershon Kedem :
Strip Layout: A New Layout Methodology for Standard Circuit Modules.
363-369
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W. Lee :
"?": A Context-Sensitive Help System Based on Hypertext.
429-435
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Bertrand Serlet :
Fast, Small, and Static Combinatorial CMOS Circuits.
451-458
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P. A. Subrahmanyam :
LCS - A Leaf Cell Synthesizer Employing Formal Deduction Techniques.
459-465
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M. Shahdad :
An Interface between VHDL and EDIF.
472-478
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Curtis H. Parks :
Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis.
479-483
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J. Hines :
Where VHDL Fits Within the CAD Environment.
491-494
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M. Ladjadj ,
J. F. McDonald :
Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits.
509-515
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Ronald Waxman :
The Design Automation Standards Environment.
559-561
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L. O'Connell :
Design Automation Standards Need Integration.
562-562
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R. J. Pachter :
Design Automation Standards - Perspectives from a Down-the-Road End User.
563-564
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M. L. Brei :
Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms.
565-565
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Larry Soulé ,
R. Blank :
Statistics for Parallelism and Abstraction Level in Digital Simulation.
588-591
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Dick C. A. Bulterman :
CASE: An Integrated Design Environment for Algorithm-Driven Architectures.
596-599
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Chin-Long Wey :
On Yield Consideration for the Design of Redundant Programmable Logic Arrays.
622-628
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D. Kaplan :
Routing with a Scanning Window-8Ma Unified Approach.
629-632
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C. H. Ng :
A "gridless" Variable-Width Channel Router for Marco Cell Design.
633-636
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R. L. Steele :
An Expert System Application in Semicustom VLSI Design.
679-688
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E. Rosenberg :
A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards.
721-726
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Jeremy Dion :
Fast Printed Circuit Board Routing.
727-734
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R. Forbes :
Heuristic Acceleration of Force-Directed Placement.
735-740
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Emil F. Girczyc ,
Tai A. Ly :
STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct.
757-763
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S. Koeppe :
Optimal Layout to Avoid CMOS Stuck-Open Faults.
829-835
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