49. DAC 2012:
San Francisco, CA, USA Patrick Groeneveld , Donatella Sciuto , Soha Hassoun (Eds.):
The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012.
ACM 2012, ISBN 978-1-4503-1199-1 E-health:
a killer application for eletronic devices?
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Rudy Lauwereins :
Biomedical electronics serving as physical environmental and emotional watchdogs.
1-5
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Design automation for things wet, small, spooky, and tamable
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Be efficient:
low-power design techniques
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Design and data security:
is it even possible?
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Domenic Forte ,
Ankur Srivastava :
On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction.
96-105
System simulation:
the need for speed!
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Can EDA combat the rise of electronic counterfeiting?
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conf/dac/KoushanfarFMBSSP12
Reliability:
from atoms to 3-D
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EDA for emerging applications at the kilometer, micron, and nanometer scales
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G. Reza Chaji ,
Javid Jaffari :
Generic low-cost characterization of Vth and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displays.
182-187
Facing dependability:
system-level solutions and cybercar challenges
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Volatile or non-volatile? that's the question
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Self-aware and adaptive technologies:
the future of computing systems?
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conf/dac/HoffmannHKLMMNSSACD12 Henry Hoffmann ,
Jim Holt ,
George Kurian ,
Eric Lau ,
Martina Maggio ,
Jason E. Miller ,
Sabrina M. Neuman ,
Mahmut E. Sinangil ,
Yildiz Sinangil ,
Anant Agarwal ,
Anantha P. Chandrakasan ,
Srinivas Devadas :
Self-aware computing in the Angstrom processor.
259-264
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conf/dac/AuerbachBBCFRS12 export record as
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Why model? beacuse reality is complicated enough!
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Yangfeng Su ,
Fan Yang ,
Xuan Zeng :
AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits.
295-300
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Arie Meir ,
Jaijeet S. Roychowdhury :
BLAST: efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric Lagrange enabled transient adjoint analysis.
301-310
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Is formal verification ready for the system level?
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Sanjit A. Seshia :
Sciduction: combining induction, deduction, and structure for verification and synthesis.
356-365
NoCs next top model:
from system-level to prototype
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Timing analysis and software-controlled memory:
are we safe?
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Luis Angel D. Bathen ,
Nikil Dutt :
HaVOC : a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories.
447-452
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Routing-driven design closure
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Gyuszi Suto :
Rule agnostic routing by using design fabrics.
471-475
Storing, computing, and storing while computing:
the new face of non-volatility in systems
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conf/dac/DinglerKNHCNPBLS12 export record as
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You can count on me:
why it's OK to be imprecise or unreliable
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conf/dac/KarakonstantisRBB12 export record as
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Optimization to the rescue of analog
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Xterminating bugs
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Brain-inspired autonomous computing and modeling
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conf/dac/Al-MaashriDCCXNC12 export record as
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Design, the next generation:
from routing to capturing design expertise
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Yanheng Zhang ,
Chris Chu :
GDRouter: interleaved global routing and detailed routing for ultimate routability.
597-602
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conf/dac/ShachamGSWBVHDQR12
Staying cool:
modeling thermal effects in 3-D and multicore
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SOS:
specification, optimization, and synthesis in system-level design
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Future of IC reliability
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conf/dac/RajendiranAPTG12 export record as
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Breaking out of EDA:
how to apply EDA techniques to broader applications
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The right placement at the right timing
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conf/dac/AthikulwongsePL12 export record as
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conf/dac/ViswanathanASLW12
Global views of synthesis:
broadening the scope
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conf/dac/VenkataramaniSKRR12 export record as
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Adaptive computing:
when, where, why, how?
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Yin and yang of memories:
the power-performance trade-off
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Probabilistic embedded computing
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Simulation-based verification:
new ways to harness the workhorse
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conf/dac/ChatterjeeKMZB12
Ultra-low power using subthreshold and nearthreshold operation
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Mingoo Seok :
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits.
968-973
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Top picks of run-time power management techiques
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The dark side of test
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Design challenges and EDA solutions for wireless sensor networks
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conf/dac/ChristmannBCWP12
Surviving timing challenges in nanometer designs
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conf/dac/ZolotovSHFVXLV12 export record as
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Special delivery:
challenges in packaging
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Renovate analog and mixed-signal circuit simulations
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Xueqian Zhao ,
Zhuo Feng :
Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners.
1119-1124
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Heterogenous platforms:
challenges and opportunities
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Michael B. Taylor :
Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse.
1131-1136
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conf/dac/MelpignanoBFJLHCD12 export record as
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Brian Jeff :
Big.LITTLE system architecture from ARM: saving power through heterogeneous multiprocessing and task context migration.
1143-1146
Hot chips running cool - energy efficient near-threshold computing and its barriers
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conf/dac/PinckneySDFMSB12 export record as
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Yielding in an uncertain world
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High-level synthesis is not just about translation!
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conf/dac/BachrachVRLWAWA12 export record as
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Jason Cong ,
Peng Zhang ,
Yi Zou :
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis.
1233-1238
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Jason Cong ,
Bin Liu :
A metric for layout-friendly microarchitecture optimization in high-level synthesis.
1239-1244
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Wild and crazy ideas
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Ian G. Harris :
Extracting design information from natural language specifications.
1256-1257
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Optimizing embedded software for high performance and reliability
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