48. DAC 2011: San Diego, CA, USA

Design methods and trends for automotive architectures

• Helge Zinner, Josef Nöbauer, Thomas Gallner, Jochen Seitz, Thomas Waas:
  Application and realization of gateways between conventional automotive and IP/ethernet-based networks. 1-6
  
• Hyung-Taek Lim, Lars Völker, Daniel Herrscher:
  Challenges in a future IP/ethernet-based in-car network for real-time applications. 7-12
  
• S. Ramesh, Ambar A. Gadkari:
  Rigorous model-based design & verification flow for in-vehicle software. 13-16
  

Performance and reliability of flash memory systems

• Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, Yong Guan:
  MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems. 17-22
  
• Li-Pin Chang, You-Chiuan Su:
  Plugging versus logging: a new approach to write buffer management for solid-state disks. 23-28
  
• Pei-Han Hsu, Yuan-Hao Chang, Po-Chun Huang, Tei-Wei Kuo, David Hung-Chang Du:
  A version-based strategy for reliability enhancement of flash file systems. 29-34
  
• Hung-Wei Tseng, Laura M. Grupp, Steven Swanson:
  Understanding the impact of power loss on flash memory. 35-40
  

System-level power management

• Yanzhi Wang, Qing Xie, Ahmed Ammari, Massoud Pedram:
  Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification. 41-46
  
• Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh:
  PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. 47-52
  
• Donghwa Shin, Younghyun Kim, Naehyuck Chang, Massoud Pedram:
  Dynamic voltage scaling of OLED displays. 53-58
  
• Hyunsun Park, Sungjoo Yoo, Sunggu Lee:
  Power management of hybrid DRAM/PRAM-based main memory. 59-64
  

Design for manufacturability

• Wing Chiu Tam, R. D. (Shawn) Blanton:
  To DFM or not to DFM? 65-70
  
• Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu:
  Self-aligned double patterning decomposition for overlay minimization and hot spot detection. 71-76
  
• Miguel Miranda, Philippe Roussel, Lucas Brusamarello, Gilson I. Wirth:
  Statistical characterization of standard cells using design of experiments with response surface modeling. 77-82
  
• Nikolai Ryzhenko, Steven Burns:
  Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. 83-88
  

Thermal management and modeling for integrated circuits

• Peter Bailis, Vijay Janapa Reddi, Sanjay Gandhi, David Brooks, Margo I. Seltzer:
  Dimetrodon: processor-level preventive thermal management via idle cycle injection. 89-94
  
• Yang Ge, Qinru Qiu:
  Dynamic thermal management for multimedia applications using machine learning. 95-100
  
• Abdullah Nazma Nowroz, Gary Woods, Sherief Reda:
  Improved post-silicon power modeling using AC lock-in techniques. 101-106
  
• Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin:
  Thermal signature: a simple yet accurate thermal index for floorplan optimization. 108-113
  

Design and synthesis of biological circuits

• Douglas Densmore, Mark Horowitz, Smita Krishnaswamy, Xiling Shen, Adam Arkin, Erik Winfree, Chris Voigt:
  Joint DAC/IWBDA special session design and synthesis of biological circuits. 114-115
  

Sweet streams, embedded in multicores

• Jiali Teddy Zhai, Hristo Nikolov, Todor Stefanov:
  Modeling adaptive streaming applications with parameterized polyhedral process networks. 116-121
  
• Weijia Che, Karam S. Chatha:
  Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming. 122-127
  
• Yooseong Kim, Aviral Shrivastava:
  CuMAPz: a tool to analyze memory access patterns in CUDA. 128-133
  
• Nabeel Iqbal, Muhammad Adnan Siddique, Jörg Henkel:
  SEAL: soft error aware low power scheduling by Monte Carlo state space under the influence of stochastic spatial and temporal dependencies. 134-139
  

Late flow optimization and rectification

• Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
  Simultaneous functional and timing ECO. 140-145
  
• Kai-Fu Tang, Chi-An Wu, Po-Kai Huang, Chung-Yang (Ric) Huang:
  Interpolation-based incremental ECO synthesis for multi-error logic rectification. 146-151
  
• Li Li, Yinghai Lu, Hai Zhou:
  Optimal multi-domain clock skew scheduling. 152-157
  
• Yuxi Liu, Feng Yuan, Qiang Xu:
  Re-synthesis for cost-efficient circuit-level timing speculation. 158-163
  

Routing revived

• Tao Huang, Evangeline F. Y. Young:
  An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles. 164-169
  
• Tim Nieberg:
  Gridless pin access in detailed routing. 170-175
  
• Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong:
  An optimal algorithm for layer assignment of bus escape routing on PCBs. 176-181
  
• Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Charles Chiang, Tsung-Yi Ho:
  A distributed algorithm for layout geometry operations. 182-187
  

It's all in the models...

• Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim:
  TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. 188-193
  
• Eva L. Dyer, Mehrdad Majzoobi, Farinaz Koushanfar:
  Hybrid modeling of non-stationary process variations. 194-199
  
• Changdao Dong, Xin Li:
  Efficient SRAM failure rate prediction via Gibbs sampling. 200-205
  
• Wenwen Chai, Dan Jiao:
  Direct matrix solution of linear complexity for surface integral-equation based impedance extraction of high bandwidth interconnects. 206-211
  

Killer apps for 3-D ICs?

• Jeff Burns, Gary Carpenter, Eren Kursun, Ruchir Puri, James Warnock, Michael Scheuermann:
  Design, CAD and technology challenges for future processors: 3D perspectives. 212
  
• Eric Beyne, Pol Marchal, Geert Van der Plas:
  3D heterogeneous system integration: application driver for 3D technology development. 213
  
• Shekhar Borkar:
  3D integration for energy efficient system design. 214-219
  
• Rasit Onur Topaloglu:
  Applications driving 3D integration and corresponding manufacturing challenges. 220-223
  

Towards embedded systems we can trust: from models to gates

• Nannan He, Philipp Rümmer, Daniel Kroening:
  Test-case generation for embedded simulink via formal concept analysis. 224-229
  
• Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
  A first step towards automatic application of power analysis countermeasures. 230-235
  
• Jared Schmitz, Jason Loew, Jesse Elwell, Dmitry Ponomarev, Nael B. Abu-Ghazaleh:
  TPM-SIM: a framework for performance evaluation of trusted platform modules. 236-241
  
• Miodrag Potkonjak, Saro Meguerdichian, Ani Nahapetian, Sheng Wei:
  Differential public physically unclonable functions: architecture and applications. 242-247
  
• Sheng Wei, Miodrag Potkonjak:
  Integrated circuit security techniques using variable supply voltage. 248-253
  
• Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner:
  Information flow isolation in I2C and USB. 254-259
  

Embedded multiprocessor software synthesis

• Bratin Saha:
  CIRUS: a scalable modular architecture for reusable drivers. 260-261
  
• Pierre G. Paulin:
  Programming challenges & solutions for multi-processor SoCs: an industrial perspective. 262-267
  
• Lothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov:
  Thermal-aware system analysis and software synthesis for embedded multi-processors. 268-273
  
• Dai N. Bui, Edward A. Lee, Isaac Liu, Hiren D. Patel, Jan Reineke:
  Temporal isolation on multiprocessing architectures. 274-279
  

Wild and crazy ideas

• Vikram Jandhyala:
  Physics-based field-theoretic design automation tools for social networks and web search. 280-281
  
• Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Paul-Henry Morel, Jean-Philippe Noël, Fabien Clermidy, Ian O'Connor:
  Can we go towards true 3-D architectures? 282-283
  
• Görschwin Fey:
  Orchestrated multi-level information flow analysis to understand SoCs. 284-285
  
• Phillip Kinsman, Nicola Nicolici:
  Dynamic binary translation to a reconfigurable target for on-the-fly acceleration. 286-287
  
• Saro Meguerdichian, Miodrag Potkonjak:
  Device aging-based physically unclonable functions. 288-289
  
• Georgios Karakonstantis, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Tziantzioulis, Vaibhav Gupta, Kaushik Roy:
  Significance driven computation on next-generation unreliable platforms. 290-291
  

Analog and mixed-signal design in an uncertain world

• Karthik V. Aadithya, Sriramkumar Venogopalan, Alper Demir, Jaijeet S. Roychowdhury:
  MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs. 292-297
  
• Fang Gong, Hao Yu, Lei He:
  Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials. 298-303
  
• Parijat Mukherjee, G. Peter Fang, Rod Burt, Peng Li:
  Automatic stability checking for large linear analog integrated circuits. 304-309
  
• Zhigang Hao, Sheldon X.-D. Tan, Ruijing Shen, Guoyong Shi:
  Performance bound analysis of analog circuits considering process variations. 310-315
  
• Xin Li:
  Rethinking memory redundancy: optimal bit cell repair for maximum-information storage. 316-321
  
• Rui Zheng, Jounghyuk Suh, Cheng Xu, Nagib Hakim, Bertan Bakkaloglu, Yu Cao:
  Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability. 322-327
  

Scaling and security: does more transistors mean more security?

• Paul Kocher:
  Complexity and the challenges of securing SoCs. 328-331
  
• Ram Krishnamurthy, Sanu Mathew, Farhana Sheikh:
  High-performance energy-efficient encryption in the sub-45nm CMOS Era. 332
  
• Randy Torrance, Dick James:
  The state-of-the-art in semiconductor reverse engineering. 333-338
  

Need for speed: system-level analysis and design

• Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay:
  A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation. 339-344
  
• Dukyoung Yun, Jinwoo Kim, Sungchan Kim, Soonhoi Ha:
  Simulation environment configuration for parallel simulation of multicore embedded systems. 345-350
  
• Eman Copty, Gila Kamhi, Sasha Novakovsky:
  Transaction level statistical analysis for efficient micro-architectural power and performance studies. 351-356
  
• Harry Broeders, René van Leuken:
  Extracting behavior and dynamically generated hierarchy from SystemC models. 357-362
  
• Huang Huang, Gang Quan, Jeffrey Fan, Meikang Qiu:
  Throughput maximization for periodic real-time systems under the maximal temperature constraint. 363-368
  
• Adrian Alin Lifa, Petru Eles, Zebo Peng:
  Performance optimization of error detection based on speculative reconfiguration. 369-374
  

Trends in system-level design space exploration and optimization

• Reinhard Schneider, Dip Goswami, Samarjit Chakraborty, Unmesh D. Bordoloi, Petru Eles, Zebo Peng:
  On the quantification of sustainability and extensibility of FlexRay schedules. 375-380
  
• Baoxian Zhao, Hakan Aydin, Dakai Zhu:
  Generalized reliability-oriented energy management for real-time embedded applications. 381-386
  
• Lin Huang, Rong Ye, Qiang Xu:
  Customer-aware task allocation and scheduling for multi-mode MPSoCs. 387-392
  
• Felix Reimann, Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
  Symbolic system synthesis in the presence of stringent real-time constraints. 393-398
  
• Hung-Yi Liu, Ilias Diakonikolas, Michele Petracca, Luca P. Carloni:
  Supervised design space exploration by compositional approximation of Pareto sets. 399-404
  
• Tiantian Liu, Yingchao Zhao, Chun Jason Xue, Minming Li:
  Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory. 405-410
  

Validation and test: the yin and yang

• Flavio M. de Paula, Amir Nahir, Ziv Nevo, Avigail Orni, Alan J. Hu:
  TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead. 411-416
  
• Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
  Testability driven statistical path selection. 417-422
  
• Mingjing Chen, Alex Orailoglu:
  Diagnosing scan clock delay faults through statistical timing pruning. 423-428
  
• Irith Pomeranz:
  Diagnosis of transition fault clusters. 429-434
  

Leakage power optimization

• Seokjoong Kim, Matthew R. Guthaus:
  Leakage-aware redundancy for reliable sub-threshold memories. 435-440
  
• Jun Zhou, Senthil Jayapal, Ben Busze, Li Huang, Jan Stuyt:
  A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library. 441-446
  
• Yongchan Ban, Jae-Seok Yang:
  Layout aware line-edge roughness modeling and poly optimization for leakage minimization. 447-452
  
• Hamed Abrishami, Jinan Lou, Jeff Qin, Juergen Froessl, Massoud Pedram:
  Post sign-off leakage power optimization. 453-458
  

Design and technology at 14nm node: myths and realities

• Vivek Singh:
  Lithography at 14nm and beyond: choices and challenges. 459
  
• Chenming Hu:
  New sub-20nm transistors: why and how. 460-463
  
• James Warnock:
  Circuit design challenges at the 14nm technology node. 464-467
  

Punctual software: it's about time

• Pratyush Kumar, Lothar Thiele:
  Cool shapers: shaping real-time tasks for improved thermal guarantees. 468-473
  
• Matthew Dellinger, Piyush Garyali, Binoy Ravindran:
  ChronOS Linux: a best-effort real-time multiprocessor Linux kernel. 474-479
  
• Matthew Kuo, Roopak Sinha, Partha S. Roop:
  Efficient WCRT analysis of synchronous programs using reachability. 480-485
  
• Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel:
  Fast and accurate source-level simulation of software timing considering complex code optimizations. 486-491
  

System verification: is formal the new normal?

• Daniel Holcomb, Bryan A. Brady, Sanjit A. Seshia:
  Abstraction-based performance verification of NoCs. 492-497
  
• Sangho Youn, Jaeha Kim, Mark Horowitz:
  Global convergence analysis of mixed-signal systems. 498-503
  
• Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin:
  Litmus tests for comparing memory consistency models: how long do they need to be? 504-509
  
• Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
  Formal hardware/software co-verification by interval property checking with abstraction. 510-515
  

Clocks and circuits

• Xuchu Hu, Matthew R. Guthaus:
  Distributed Resonant clOCK grid Synthesis (ROCKS). 516-521
  
• Deokjin Joo, Taewhan Kim:
  WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. 522-527
  
• Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang:
  Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. 528-533
  
• Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
  Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. 534-539
  

Model reduction and accelerated extraction

• Amit Hochman, Bradley N. Bond, Jacob K. White:
  A stabilized discrete empirical interpolation method for model reduction of electrical, thermal, and microelectromechanical systems. 540-545
  
• Zuochang Ye, Yang Li, Mingzhi Gao, Zhiping Yu:
  A novel framework for passive macro-modeling. 546-551
  
• Yu-Chung Hsiao, Luca Daniel:
  A highly scalable parallel boundary element method for capacitance extraction. 552-557
  
• Xueqian Zhao, Zhuo Feng:
  Fast multipole method on GPU: tackling 3-D capacitance extraction on massively parallel SIMD platforms. 558-563
  

Pre-silicon verification methods for post-silicon validation

• Eli Singerman, Yael Abarbanel, Sean Baartmans:
  Transaction based pre-to-post silicon validation. 564-568
  
• Allon Adir, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann:
  Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor. 569-574
  
• Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell:
  A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. 575-578
  

Embedded systems case studies and design methods

• Yoon Seok Yang, Pankaj Bhagawat, Gwan Choi:
  Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system. 579-584
  
• Srinidhi Kestur, Kevin M. Irick, Sungho Park, Ahmed Al-Maashri, Vijaykrishnan Narayanan, Chaitali Chakrabarti:
  An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. 585-590
  
• Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
  A low-energy computation platform for data-driven biomedical monitoring algorithms. 591-596
  
• Andreas Kern, Helge Zinner, Thilo Streichert, Josef Nöbauer, Jürgen Teich:
  Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks. 597-602
  
• Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
  Dynamic effort scaling: managing the quality-efficiency tradeoff. 603-608
  
• Byungchul Hong, Chulho Shin, Daehyup Ko:
  Emulation based high-accuracy throughput estimation for high-speed connectivities: case study of USB2.0. 609-614
  

Logic synthesis: old stories with new twists

• Stergios Stergiou:
  Implicit permutation enumeration networks and binary decision diagrams reordering. 615-620
  
• Ting-Hao Lin, Chung-Yang (Ric) Huang:
  Using SAT-based Craig interpolation to enlarge clock gating functions. 621-626
  
• Mohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen:
  Power reduction via separate synthesis and physical libraries. 627-632
  
• Alberto Puggelli, Tobias Welp, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli:
  Are logic synthesis tools robust? 633-638
  

3-D IC design

• Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
  Layout effects in fine grain 3D integrated regular microprocessor blocks. 639-644
  
• Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang:
  Fault-tolerant 3D clock network. 645-651
  
• Xiaodong Liu, Yifan Zhang, Gary K. Yeap, Xuan Zeng:
  An integrated algorithm for 3D-IC TSV assignment. 652-657
  
• Bing Shi, Ankur Srivastava, Peng Wang:
  Non-uniform micro-channel design for stacked 3D-ICs. 658-663
  
• Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov:
  TSV-aware analytical placement for 3D IC designs. 664-669
  
• Jason Cong, Guojie Luo, Yiyu Shi:
  Thermal-aware cell and through-silicon-via co-placement for 3D ICs. 670-675
  

Advancement in power integrity and circuit reliability

• Pei Sun, Xin Li, Ming Yuan Ting:
  Efficient incremental analysis of on-chip power grid via sparse approximation. 676-681
  
• Nahi H. Abdul Ghani, Farid N. Najm:
  Power grid verification using node and branch dominance. 682-687
  
• Pamela Al Haddad, Farid N. Najm:
  Power grid correction using sensitivity analysis under an RC model. 688-693
  
• Jyothi Velamala, Robert LiVolsi, Myra Torres, Yu Cao:
  Design sensitivity of single event transients in scaled logic circuits. 694-699
  
• Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg:
  Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors. 700-705
  
• Shuo Wang, Mohammad Tehranipoor, LeRoy Winemberg:
  In-field aging measurement and calibration for power-performance optimization. 706-711
  

CMOS sensors for biomedical and biological applications

• Sebastian Sorgenfrei, Kenneth L. Shepard:
  Single-molecule electronic detection using nanoscale field-effect devices. 712-717
  
• Eric Stern, David A. Routenberg, Aleksandar Vacic, Nitin K. Rajan, Jason M. Criscione, Jason Park, Tarek M. Fahmy, Mark Reed:
  CMOS compatible nanowires for biosensing. 718-722
  
• Sameer Sonkusale, Mehmet Dokmeci:
  Heterogeneous integration of carbon nanotubes and graphene microassemblies for environmental and breath sensing. 723-728
  

Novel architectures and algorithms for multiprocessor and biological applications

• Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan:
  An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. 729-734
  
• Zheng Li, Moustafa Mohamed, Xi Chen, Alan Rolf Mickelson, Li Shang:
  Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance. 735-740
  
• Tsung-Wei Huang, Hong-Yan Su, Tsung-Yi Ho:
  Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips. 741-746
  
• Renato Umeton, Giovanni Stracquadanio, Anilkumar Sorathiya, Pietro Liò, Alessio Papini, Giuseppe Nicosia:
  Design of robust metabolic pathways. 747-752
  

New methods and metrics in test and reliability

• Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, Chih-Tsun Huang:
  Reliability analysis and improvement for multi-level non-volatile memories with soft information. 753-758
  
• Hsiu-Ming Chang, Kwang-Ting (Tim) Cheng:
  Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers. 759-764
  
• Leyi Yin, Yongtae Kim, Peng Li:
  High effective-resolution built-in jitter characterization with quantization noise shaping. 765-770
  
• Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chiou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
  A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. 771-776
  

CAD techniques for advanced process technologies

• Sari Onaissi, Feroze Taraporevala, Jinfeng Liu, Farid N. Najm:
  A fast approach for static timing analysis covering all PVT corners. 777-782
  
• Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim:
  Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. 783-788
  
• Yongchan Ban, Kevin Lucas, David Z. Pan:
  Flexible 2D layout decomposition framework for spacer-type double pattering lithography. 789-794
  
• Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan:
  AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection. 795-800
  

Repurposing I.C. CAD computational techniques for molecular and cell biology

• Jaydeep P. Bardhan, Andreas Hildebrandt:
  A fast solver for nonlocal electrostatic theory in biomolecular science and engineering. 801-805
  
• Jared E. Toettcher, Anya Castillo, Bruce Tidor, Jacob White:
  Biochemical oscillator sensitivity analysis in the presence of conservation constraints. 806-811
  
• Marisa Eisenberg, Joshua N. Ash, Dan Siegal-Gaskins:
  In silico synchronization of cellular populations through expression data deconvolution. 812-817
  

Computing fabrics: cores, LUTs, and molecules

• Senthilkumar Thoravi Rajavel, Ali Akoglu:
  MO-pack: many-objective clustering for FPGA CAD. 818-823
  
• Nikhil A. Patil, Ankit Bansal, Derek Chiou:
  Enforcing architectural contracts in high-level synthesis. 824-829
  
• Liang Chen, Tulika Mitra:
  Shared reconfigurable fabric for multi-core customization. 830-835
  
• Hua Jiang, Marc D. Riedel, Keshab K. Parhi:
  Synchronous sequential computation with molecular reactions. 836-841
  

Outsmarting bugs through intelligent simulation

• Wisam Kadry, Ronny Morad, Alex Goryachev, Eli Almog, Christopher A. Krygowski:
  Facing the challenge of new design features: an effective verification approach. 842-847
  
• Yoav Katz, Michal Rimon, Avi Ziv, Gai Shaked:
  Learning microarchitectural behaviors to improve stimuli generation quality. 848-853
  
• Michael D. Moffitt, Mátyás A. Sustik, Paul G. Villarrubia:
  Robust partitioning for hardware-accelerated functional verification. 854-859
  
• Allon Adir, Maxim Golubev, Shimon Landa, Amir Nahir, Gil Shurek, Vitali Sokhin, Avi Ziv:
  Threadmill: a post-silicon exerciser for multi-threaded processors. 860-865
  

Novel design and analysis tools for emerging devices

• Chun-Yi Lee, Niraj K. Jha:
  CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. 866-871
  
• Michael B. Henry, Meeta Srivastav, Leyla Nazhandali:
  A case for NEMS-based functional-unit power gating of low-power embedded microprocessors. 872-877
  
• Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
  Automated mapping for reconfigurable single-electron transistor arrays. 878-883
  
• Andrew Zukoski, Xuebei Yang, Kartik Mohanram:
  Universal logic modules based on double-gate carbon nanotube transistors. 884-889
  

Virtualization in embedded systems

• Joshua S. Auerbach, David F. Bacon, Perry Cheng, Rodric M. Rabbah, Sunil Shukla:
  Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language. 890-894
  
• Kim M. Hazelwood:
  Process-level virtualization for runtime adaptation of embedded software. 895-900
  
• Gernot Heiser:
  Virtualizing embedded systems: why bother? 901-905
  
• Jan Vitek:
  Virtualizing real-time embedded systems with Java. 906-911
  

Towards reliable and energy-minimal NOC design

• Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh:
  DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips. 912-917
  
• Wen-Chung Tsai, Deng-Yuan Zheng, Sao-Jie Chen, Yu Hen Hu:
  A fault-tolerant NoC scheme using bidirectional channel. 918-923
  
• Akbar Sharifi, Mahmut T. Kandemir:
  Process variation-aware routing in NoC based multicores. 924-929
  
• Konstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiuan Peh:
  Enabling system-level modeling of variation-induced faults in networks-on-chips. 930-935
  
• Gwangsun Kim, John Kim, Sungjoo Yoo:
  FlexiBuffer: reducing leakage power in on-chip network routers. 936-941
  
• Isask'har Walter, Erez Kantor, Israel Cidon, Shay Kutten:
  Capacity optimized NoC for multi-mode SoC. 942-947
  

Don't forget memory: performance and reliability issues in cache, scratchpad, and PRAM

• Weixun Wang, Prabhat Mishra, Sanjay Ranka:
  Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems. 948-953
  
• Mahmut T. Kandemir, Taylan Yemliha, Emre Kultursay:
  A helper thread based dynamic cache partitioning scheme for multithreaded applications. 954-959
  
• Jason Cong, Hui Huang, Chunyue Liu, Yi Zou:
  A reuse-aware prefetching scheme for scratchpad memory. 960-965
  
• Carlos Flores Fajardo, Zhen Fang, Ravi Iyer, German Fabila Garcia, Seung Eun Lee, Li Zhao:
  Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. 966-971
  
• Jianbo Dong, Lei Zhang, Yinhe Han, Ying Wang, Xiaowei Li:
  Wear rate leveling: lifetime enhancement of PRAM with endurance variation. 972-977
  
• Young-Geun Choi, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn:
  Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache. 978-983
  

Ultra-low voltage and power-aware design

• Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
  A closed-form expression for estimating minimum operating voltage (V_DDmin) of CMOS logic gates. 984-989
  
• Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester:
  Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. 990-995
  
• Selçuk Köse, Eby G. Friedman:
  Fast algorithms for IR voltage drop analysis exploiting locality. 996-1001
  
• Tong Xu, Peng Li, Boyuan Yan:
  Decoupling for power gating: sources of power noise and design strategies. 1002-1007
  
• Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
  Error-resilient low-power DSP via path-delay shaping. 1008-1013
  
• Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici:
  Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. 1014-1019
  

Specialized processing systems for embedded computing

• Jason Clemons, Andrew Jones, Robert Perricone, Silvio Savarese, Todd M. Austin:
  EFFEX: an embedded processor for computer vision based feature extraction. 1020-1025
  
• Bruno Zatt, Muhammad Shafique, Felipe Sampaio, Luciano Volcan Agostini, Sergio Bampi, Jörg Henkel:
  Run-time adaptive energy-aware motion and disparity estimation in multiview video coding. 1026-1031
  
• Haris Javaid, Muhammad Shafique, Sri Parameswaran, Jörg Henkel:
  Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. 1032-1037
  
• Muhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic:
  RJOP: a customized Java processor for reactive embedded systems. 1038-1043
  
• Yuhao Zhu, Yangdong Deng, Yubei Chen:
  Hermes: an integrated CPU/GPU microarchitecture for IP routing. 1044-1049
  
• Avadh Patel, Furat Afram, Shunfei Chen, Kanad Ghose:
  MARSS: a full system simulator for multicore x86 CPUs. 1050-1055
  

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