William H. Joyner Jr., Grant Martin, Andrew B. Kahng (Eds.):
Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005.
ACM 2005, ISBN 1-59593-058-2
42. DAC 2005:
San Diego, CA, USA
Microarchitecture-level power analysis and optimization techniques
Leakage analysis and optimization
, John P. Hayes
: Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages.
, Gang Qu
: Enhanced leakage reduction Technique by gate replacement.
, Alex Doboli
: Systematic development of analog circuit structural macromodels through behavioral model decoupling.
Statistical timing analysis
Advances in design-for-testability methods
Advances in boundary element methods for parasitic extraction
Management Day Session
, Yi Zhao
, Sujit Dey
: Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits.
Physical considerations in high-level synthesis
Architectures for cryptography and security applications
Performance, energy, and fault-tolerance considerations for MPSoC designs
Management Day Session
losing the power gap between ASIC and custom
information design methodology
Statistical optimization and manufacturability
Application specific architecture design tools
Ho Young Kim
, Tag Gon Kim
: Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse.
what went wrong!
Design methods for manufacturability enhancements
Methods and representations for logic synthesis
, Munehiro Matsuura
: BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition.
Generating efficient models for analog circuits
: Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits.
emerging directions in wireless
CAD for FPGAs
Effective formal verification using word-level reasoning, bit-level generality, and parallelism
Advances in synthesis
Coping with buffering
Impact of process variations on power
The best of wireless at ISSCC
, Hugh Mair
, Franck Dahan
, Mike Wagner
, Mark Streeter
, Laurent Bouetel
, Joel Blasquez
, H. Clasen
, G. Semino
, Julie Dong
, D. Scott
, B. Pitts
, Claudine Raibaut
, Uming Ko
: A design platform for 90-nm leakage reduction techniques.
Architectural support for communication
New approaches to physical design problems
MATLAB - the other emerging system-design language
David P. Magee
: Matlab extensions for the development, testing and verification of real-time DSP software.
Emerging ideas in energy management techniques
, Pai H. Chou
: Application/architecture power co-optimization for embedded systems powered by renewable sources.
Advances in optimization of mixed-signal circuits
Circuit performance under parameter variation
Formally verifying your 10-million gate design
: Can we really do without the support of formal methods in the verification of large designs?
: Streamline verification process with formal property verification to meet highly compressed design cycle.
Embedded hardware and system software
: Frequency-based code placement for embedded multiprocessors.
Power estimation and design tradeoffs
, Lei He
: Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.
cool algorithms and hot applications
DFM and variability:
Theory and practice
Farid N. Najm
: On the need for statistical timing analysis.
Tools and methods for the verification of processors and processor-based systems
Electrical optimization for physical synthesis
, Xun Liu
: Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method.
Optimization techniques in high-level synthesis
: Towards scalable flow and context sensitive pointer analysis.
Testing for process- and timing-related faults
Hierarchical design and design space exploration of analog integrated circuits
Dynamic voltage scaling
New directions in FPGA technologies