42. DAC 2005: San Diego, CA, USA


Error-tolerant design

Microarchitecture-level power analysis and optimization techniques

Leakage analysis and optimization

Analog macromodeling


Statistical timing analysis

Embedded software

Advances in design-for-testability methods

Advances in boundary element methods for parasitic extraction

Management Day Session


Physical considerations in high-level synthesis

Architectures for cryptography and security applications

Performance, energy, and fault-tolerance considerations for MPSoC designs

Management Day Session

losing the power gap between ASIC and custom


Wireless session: information design methodology

Statistical optimization and manufacturability

Application specific architecture design tools

The Titanic: what went wrong!


Design methods for manufacturability enhancements

Methods and representations for logic synthesis

Generating efficient models for analog circuits

Special session: emerging directions in wireless


Effective formal verification using word-level reasoning, bit-level generality, and parallelism

Advances in synthesis

Coping with buffering


Impact of process variations on power

Special session: The best of wireless at ISSCC

Architectural support for communication

New approaches to physical design problems

Special session: MATLAB™ - the other emerging system-design language


Emerging ideas in energy management techniques

Advances in optimization of mixed-signal circuits

Circuit performance under parameter variation

Special session: Formally verifying your 10-million gate design

Embedded hardware and system software

Power estimation and design tradeoffs