39. DAC 2002:
New Orleans, LA, USA Wall street evaluates EDA
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Web and IP based design
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Design innovations for embedded processors
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Passive model order reduction
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New perspectives in physical design
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Panel:
Tools or Users:
Which is the Bigger Bottleneck?
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Life after CMOS:
Imminent or Irrelevant?
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H. Bernhard Pogge :
The next chip challenge: effective methods for viable mixed technology SoCs.
84-87
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Formal verification
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High level specification and design
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Kerstin Eder ,
Geoff Barrett :
Achieving maximum performance: a method for the verification of interlocked pipeline control logic.
135-140
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conf/dac/ChakrabartiDCB02
Timing abstraction
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Hiroyuki Higuchi :
An implication-based method to detect multi-cycle paths in large sequential circuits.
164-169
E-textiles
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Panel:
Analog Intellectual Property:
Now? Or Never?
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Low-power system design
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Fabric-driven logic synthesis
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Memory management and address optimization in embedded systems
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Optics:
lighting the way to EDA riches?
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Edward H. Sargent :
Multifunctional photonic integration for the agile optical internet.
231-234
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PANEL:
Nanometer Design:
What Hurts Next...?
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conf/dac/BrodersenHKKLK02
Novel DFT, BIST and diagnosis techniques
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Case studies in embedded system design
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Hyunok Oh ,
Soonhoi Ha :
Efficient code synthesis from extended dataflow graphs for multimedia applications.
275-280
Theoretical foundations of embedded system design
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Ingo Sander ,
Axel Jantsch :
Transformation based communication and clock domain refinement for system design.
281-286
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Equivalence verification
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conf/dac/AnastasakisDMS02 export record as
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PANEL:
Whither (or Wither?) ASIC Handoff
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conf/dac/SantariniJMEKRRY02
Embedded software automation:
from specification to binary
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Applications of reconfigurable computing
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New test methods targeting non-classical faults
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How Do You Design a 10M Gate ASIC?
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Christian Berthet :
Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry.
375-378
Power distribution issues
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conf/dac/BadarogluTDWMVG02
Advances in synthesis
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Christos P. Sotiriou :
Implementing asynchronous circuits using a conventional EDA tool-flow.
415-418
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Analog synthesis & design methodology
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conf/dac/VandenbusscheULSG02
Low-power physical design
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PANEL:
Unified Tools for SoC Embedded Systems:
Mission Critical, Mission Impossible or Mission Irrelevant?
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Multi-voltage, multi-threshold design
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Advanced simulation techniques
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Michael H. Perrott :
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.
498-503
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Baolin Yang ,
Joel R. Phillips :
Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method.
504-509
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Giorgio Casinovi :
An algorithm for frequency-domain noise analysis in nonlinear systems.
514-517
Design methodologies meet network applications
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conf/dac/Ykman-CouvreurLVCNK02 export record as
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Advances in analog modeling
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Yehia Massoud ,
Jacob White :
Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials.
552-555
Advances in timing and simulation
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Formal Verification Methods:
Getting around the Brick Wall
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Routing and buffering
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System on chip design
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Robert Siegmund ,
Dietmar Müller :
A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications.
602-607
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Timing analysis and memory optimization for embedded systems
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conf/dac/ChakrabortyEKT02 export record as
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Processors and accelerators for embedded applications
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conf/dac/RichardsonHHZSL02 export record as
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PANEL:
What's the Next EDA Driver?
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Cross-talk noise analysis and management
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Byron Krauter ,
David Widiger :
Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax.
665-668
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Test cost reduction for SOCS
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Scheduling techniques for embedded systems
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Designing SoCs for yield improvement
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Yervant Zorian :
Embedding infrastructure IP for SOC yield improvement.
709-712
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Advances in SAT
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Inductance and substrate analysis
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Development of processors and communication networks for embedded systems
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conf/dac/CesarioBGLNPYJD02 export record as
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Moving towards more effective validation
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Energy efficient mobile computing
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Floorplanning and placement
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Ke Zhong ,
Shantanu Dutt :
Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control.
854-859
Circuit effects in static timing
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Bernard N. Sheehan :
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells.
866-869
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Design space exploration for embedded systems
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Behavioral synthesis
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