39. DAC 2002: New Orleans, LA, USA

Wall street evaluates EDA

Web and IP based design

Design innovations for embedded processors

Passive model order reduction

New perspectives in physical design

Panel: Tools or Users: Which is the Bigger Bottleneck?

Life after CMOS: Imminent or Irrelevant?

Formal verification

High level specification and design

Timing abstraction


Panel: Analog Intellectual Property: Now? Or Never?

Low-power system design

Fabric-driven logic synthesis

Memory management and address optimization in embedded systems

Optics: lighting the way to EDA riches?

PANEL: Nanometer Design: What Hurts Next...?

Novel DFT, BIST and diagnosis techniques

Case studies in embedded system design

Theoretical foundations of embedded system design

Equivalence verification

PANEL: Whither (or Wither?) ASIC Handoff

Embedded software automation: from specification to binary

Applications of reconfigurable computing

New test methods targeting non-classical faults

How Do You Design a 10M Gate ASIC?

Power distribution issues

Advances in synthesis

Analog synthesis & design methodology

Low-power physical design

PANEL: Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant?

Multi-voltage, multi-threshold design

Advanced simulation techniques

Design methodologies meet network applications

Advances in analog modeling

Advances in timing and simulation

Formal Verification Methods: Getting around the Brick Wall

Routing and buffering

System on chip design

Timing analysis and memory optimization for embedded systems

Processors and accelerators for embedded applications

PANEL: What's the Next EDA Driver?

Cross-talk noise analysis and management

Test cost reduction for SOCS

Scheduling techniques for embedded systems

Designing SoCs for yield improvement

Advances in SAT

Inductance and substrate analysis

Development of processors and communication networks for embedded systems